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Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.9.1 Subject: Re: [PATCH] arm64/mm: don't WARN when alloc/free-ing device private pages Content-Language: en-US From: John Hubbard To: Ard Biesheuvel CC: Andrew Morton , Catalin Marinas , Will Deacon , Anshuman Khandual , Mark Rutland , Kefeng Wang , Feiyang Chen , Alistair Popple , Ralph Campbell , , LKML , , References: <20230406040515.383238-1-jhubbard@nvidia.com> <8dd0e252-8d8b-a62d-8836-f9f26bc12bc7@nvidia.com> In-Reply-To: <8dd0e252-8d8b-a62d-8836-f9f26bc12bc7@nvidia.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.126.231.37] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT078:EE_|DM4PR12MB6399:EE_ X-MS-Office365-Filtering-Correlation-Id: d3b929f4-4eb0-431c-08ee-08db3a3739c3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Apr 2023 02:48:26.8346 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d3b929f4-4eb0-431c-08ee-08db3a3739c3 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT078.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6399 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 4/10/23 00:39, John Hubbard wrote: >> pfn_to_page(x) for values 0xc00_0000 < x < 0x1000_0000 will produce a >> kernel VA that points outside the region set aside for the vmemmap. >> This region is currently unused, but that will likely change soon. >> > > I tentatively think I'm in this case right now. Because there is no wrap > around happening in my particular config, which is CONFIG_ARM64_VA_BITS > == 48, and PAGE_SIZE == 4KB and sizeof(struct page) == 64 (details > below). > Correction, actually it *is* wrapping around, and ending up as a bogus user space address, as you said it would when being above the range: page_to_pfn(0xffffffffaee00000): 0x0000000ffec38000 > It occurs to me that ZONE_DEVICE and (within that category) device > private page support need only support rather large setups. On x86, it > requires 64-bit. And on arm64, from what I'm learning after a day or so > of looking around and comparing, I think we must require at least 48 bit > VA support. Otherwise there's just no room for things. I'm still not sure of how to make room, but working on it. thanks, -- John Hubbard NVIDIA