From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2000C394463; Fri, 10 Jul 2026 07:13:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783667604; cv=none; b=rvspKHqUmvhZP8EKx4vpk+TEKaQPrqDI6gnP9rIEanm2SKJEAWt4WO/zH88YDkCfaHgkBee8Jw2ER25beXLxlnkv3Tp8Ra7YNFGE4tLKZkybeQyVQLfLVE/lFTb1w83PPHo4NT3Ey037VcqFLSWYRCpeVAciNo/I0sKvfVbN6I8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783667604; c=relaxed/simple; bh=F+acnhbkSnT+dHWE3DY+MPKABX5PUoxxxPHmIYpzcvk=; h=Message-ID:Date:MIME-Version:Subject:To:References:From: In-Reply-To:Content-Type; b=OPfnC+rIidtk8AAPuTrUdKzmRaora/qhWkIwqCrwStQ33PqstKI5sJhKRgOL4+Ue4W9MjjnJxr9bgIVntEhLvAyFmx8GT5V+Iyf/ZGholSTm5cdBuEVIrrf29f3nGNZitB9eLKF8boY/RBU6m6hBZTlseLyVq5fn8pPHz+5Fk+Q= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ksoolnFI; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ksoolnFI" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E6B611F000E9; Fri, 10 Jul 2026 07:13:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1783667602; bh=E57FZrou9F2hFPlQ8f8FZGqm8xkBMesJIoAgHQMthH0=; h=Date:Subject:To:References:From:In-Reply-To; b=ksoolnFI8uag7ZQPrgBlWgbcqp9HsrgL29swZ1ML07ul4xBMNFGNt8oFR+J+86+gU QQWyCK/ARTWeXzySgi2IrKT4iQdmXU2u2z/+LOr85iw7R7/Wqi6vu5GAPKCsh0ZVKG U6BPw8wfmMm+jkbtDavJTvaEdeE1mE9OeYMiie6qpFpbaQvQLRgV2Cqaw0TmtC0qDe IeC1VjxsZg7ThSMK3P+wDPqC+/f687WC2bcsNziByG5sSXlqAvyuG8ZeTwFtITyQW8 NcICA+gx3ZFiIfnoAOnv6IQOqyxBPrWGWlpVwmGy2vdDLvDhqGRoLvTrwGk9k2IX2u Ui8sX78pIlIWw== Message-ID: <9062ca8c-e29d-4958-a3d3-c86e2a6a9e86@kernel.org> Date: Fri, 10 Jul 2026 09:13:16 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 4/4] serial: 8250: Add Airoha SoC UART and HSUART support To: Christian Marangi , Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , =?UTF-8?Q?Ilpo_J=C3=A4rvinen?= , Andy Shevchenko , Benjamin Larsson , John Ogness , Marco Felsch , Gerhard Engleder , Jiaxun Yang , Randy Dunlap , Binbin Zhou , Rong Zhang , Lukas Wunner , Lubomir Rintel , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org References: <20260709205656.319531-1-ansuelsmth@gmail.com> <20260709205656.319531-5-ansuelsmth@gmail.com> Content-Language: en-US From: Jiri Slaby Autocrypt: addr=jirislaby@kernel.org; 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charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 09. 07. 26, 22:56, Christian Marangi wrote: ... > --- /dev/null > +++ b/drivers/tty/serial/8250/8250_airoha.c > @@ -0,0 +1,190 @@ ... > +struct airoha_8250_priv { > + int line; > +}; > + > +struct airoha_8250_data { Do you need this struct at all? Can't you pass the type as data directly (using cast)? > + unsigned int type; > +}; > + > +struct airoha_8250_clk_div_info { > + int div; > + int mask; Perhaps make them unsigned to avoid signed arithmetics? > +}; > + > +#define UART_BRDL_20M 0x01 > +#define UART_BRDH_20M 0x00 > + > +#define XINDIV_CLOCK 20000000 > +#define XYD_Y 65000 > + > +static const struct airoha_8250_clk_div_info airoha_clk_div_info[] = { > + { .div = 10, .mask = BIT(2) }, > + { .div = 4, .mask = BIT(1) }, > + { .div = 2, .mask = BIT(0) }, > +}; > + > +static const int clock_div_tab[] = { 10, 4, 2}; > +static const int clock_div_reg[] = { 4, 2, 1}; unsigned? > + > +/* > + * Airoha UART baud rate calculation logic > + * > + * crystal_clock = 20 MHz (fixed frequency) > + * xindiv_clock = crystal_clock / clock_div > + * (x/y) = XYD, 32 bit register with 16 bits of x and then 16 bits of y > + * clock_div = XINCLK_DIVCNT (default set to 10 (0x4)), > + * - 3 bit register [ 1, 2, 4, 8, 10, 12, 16, 20 ] > + * > + * baud_rate = ((xindiv_clock) * (x/y)) / ([BRDH,BRDL] * 16) > + * > + * Selecting divider needs to fulfill > + * 1.8432 MHz <= xindiv_clk <= APB clock / 2 > + * The clocks are unknown but a divider of value 1 did not result in a valid > + * waveform. > + * > + * XYD_y seems to need to be larger then XYD_x for proper waveform generation. > + * Setting [BRDH,BRDL] to [0,1] and XYD_y to 65000 gives even values > + * for usual baud rates. > + */ > +static void airoha_set_termios(struct uart_port *port, struct ktermios *termios, > + const struct ktermios *old) > +{ > + const struct airoha_8250_clk_div_info *clk_div_info; > + struct uart_8250_port *up = up_to_u8250p(port); > + unsigned int xyd_x, nom, denom; > + unsigned int baud; > + int i; > + > + serial8250_do_set_termios(port, termios, old); > + > + baud = serial8250_get_baud_rate(port, termios, old); > + > + /* Set DLAB to access the baud rate divider registers (BRDH, BRDL) */ > + serial_port_out(port, UART_LCR, up->lcr | UART_LCR_DLAB); > + > + /* Set baud rate calculation defaults (BRDIV ([BRDH,BRDL]) to 1) */ > + serial_port_out(port, UART_AIROHA_BRDL, UART_BRDL_20M); > + serial_port_out(port, UART_AIROHA_BRDH, UART_BRDH_20M); > + > + /* > + * Calculate XYD_x and XINCLKDR register by searching > + * through a table of crystal_clock divisors. > + */ > + for (i = 0 ; i < ARRAY_SIZE(airoha_clk_div_info) ; i++) { > + clk_div_info = &airoha_clk_div_info[i]; > + > + denom = (XINDIV_CLOCK / 40) / clk_div_info->div; > + nom = baud * (XYD_Y / 40); Are these "/ 40" to avoid overflow? Add a comment. > + xyd_x = ((nom / denom) << 4); * don't you want to round to closest instead of down? * I don't understand the purpose of the shift though. > + /* For the HSUART xyd_x needs to be scaled by a factor of 2 */ > + if (port->type == UART_PORT_AIROHA_HS) > + xyd_x = xyd_x >> 1; Do not use shifts for div/mul. > + if (xyd_x < XYD_Y) > + break; > + } > + > + serial_port_out(port, UART_AIROHA_XINCLKDR, clk_div_info->mask); > + serial_port_out(port, UART_AIROHA_XYD, (xyd_x << 16) | XYD_Y); > + > + /* unset DLAB */ > + serial_port_out(port, UART_LCR, up->lcr); > +} thanks, -- js suse labs