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Thu, 27 Mar 2025 22:34:17 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGcD4IHX1W6f3V7a/135vsdoU5XAVFg/3bKjgHWhLDGDdOc4qwiWlsAX+wTGlesaJO8h2QWrQ== X-Received: by 2002:a17:902:db0a:b0:224:23be:c569 with SMTP id d9443c01a7336-22804845097mr102527305ad.22.1743140057391; Thu, 27 Mar 2025 22:34:17 -0700 (PDT) Received: from [10.92.192.202] ([202.46.23.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2291eec6f91sm9510475ad.17.2025.03.27.22.34.12 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 27 Mar 2025 22:34:16 -0700 (PDT) Message-ID: <92c4854d-033e-c7b5-ca92-cf44a1a8c0cc@oss.qualcomm.com> Date: Fri, 28 Mar 2025 11:04:11 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Subject: Re: [PATCH v8 4/4] PCI: dwc: Add support for configuring lane equalization presets Content-Language: en-US To: Manivannan Sadhasivam Cc: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Helgaas , Jingoo Han , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=c5=84ski?= , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, quic_mrana@quicinc.com, quic_vbadigan@quicinc.com References: <20250316-preset_v6-v8-0-0703a78cb355@oss.qualcomm.com> <20250316-preset_v6-v8-4-0703a78cb355@oss.qualcomm.com> <3sbflmznjfqpcja52v6bso74vhouv7ncuikrba5zlb74tqqb5u@ovndmib3kgqf> From: Krishna Chaitanya Chundru In-Reply-To: <3sbflmznjfqpcja52v6bso74vhouv7ncuikrba5zlb74tqqb5u@ovndmib3kgqf> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=fJk53Yae c=1 sm=1 tr=0 ts=67e634db cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=j4ogTh8yFefVWWEFDRgCtg==:17 a=IkcTkHD0fZMA:10 a=Vs1iUdzkB0EA:10 a=EUspDBNiAAAA:8 a=wBt9fhMRhOodALO6grUA:9 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 X-Proofpoint-GUID: F-Pksyot7O5bRcHTfmg_xhsw9o9Ye1sD X-Proofpoint-ORIG-GUID: F-Pksyot7O5bRcHTfmg_xhsw9o9Ye1sD X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-28_02,2025-03-27_02,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 mlxscore=0 mlxlogscore=999 clxscore=1015 phishscore=0 lowpriorityscore=0 bulkscore=0 malwarescore=0 suspectscore=0 spamscore=0 adultscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2503280036 On 3/28/2025 10:23 AM, Manivannan Sadhasivam wrote: > On Sun, Mar 16, 2025 at 09:39:04AM +0530, Krishna Chaitanya Chundru wrote: >> PCIe equalization presets are predefined settings used to optimize >> signal integrity by compensating for signal loss and distortion in >> high-speed data transmission. >> >> Based upon the number of lanes and the data rate supported, write >> the preset data read from the device tree in to the lane equalization >> control registers. >> >> Signed-off-by: Krishna Chaitanya Chundru >> --- >> drivers/pci/controller/dwc/pcie-designware-host.c | 60 +++++++++++++++++++++++ >> drivers/pci/controller/dwc/pcie-designware.h | 3 ++ >> include/uapi/linux/pci_regs.h | 3 ++ >> 3 files changed, 66 insertions(+) >> >> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c >> index dd56cc02f4ef..7c6e6a74383b 100644 >> --- a/drivers/pci/controller/dwc/pcie-designware-host.c >> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c >> @@ -507,6 +507,10 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) >> if (pci->num_lanes < 1) >> pci->num_lanes = dw_pcie_link_get_max_link_width(pci); >> >> + ret = of_pci_get_equalization_presets(dev, &pp->presets, pci->num_lanes); >> + if (ret) >> + goto err_free_msi; >> + >> /* >> * Allocate the resource for MSG TLP before programming the iATU >> * outbound window in dw_pcie_setup_rc(). Since the allocation depends >> @@ -808,6 +812,61 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) >> return 0; >> } >> >> +static void dw_pcie_program_presets(struct dw_pcie_rp *pp, enum pci_bus_speed speed) >> +{ >> + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); >> + u8 lane_eq_offset, lane_reg_size, cap_id; >> + u8 *presets; >> + u32 cap; >> + int i; >> + >> + if (speed == PCIE_SPEED_8_0GT) { >> + presets = (u8 *)pp->presets.eq_presets_8gts; >> + lane_eq_offset = PCI_SECPCI_LE_CTRL; >> + cap_id = PCI_EXT_CAP_ID_SECPCI; >> + /* For data rate of 8 GT/S each lane equalization control is 16bits wide*/ >> + lane_reg_size = 0x2; >> + } else if (speed == PCIE_SPEED_16_0GT) { >> + presets = pp->presets.eq_presets_Ngts[EQ_PRESET_TYPE_16GTS - 1]; >> + lane_eq_offset = PCI_PL_16GT_LE_CTRL; >> + cap_id = PCI_EXT_CAP_ID_PL_16GT; >> + lane_reg_size = 0x1; >> + } else { > > Can you add conditions for other data rates also? Like 32, 64 GT/s. If > controller supports them and if the presets property is defined in DT, then you > should apply the preset values. > > If the presets property is not present in DT, then below 'PCI_EQ_RESV' will > safely return. > I am fine to add it, but there is no GEN5 or GEN6 controller support added in dwc, isn't it best to add when that support is added and tested. - Krishna Chaitanya. >> + return; >> + } >> + >> + if (presets[0] == PCI_EQ_RESV) >> + return; >> + >> + cap = dw_pcie_find_ext_capability(pci, cap_id); >> + if (!cap) >> + return; >> + >> + /* >> + * Write preset values to the registers byte-by-byte for the given >> + * number of lanes and register size. >> + */ >> + for (i = 0; i < pci->num_lanes * lane_reg_size; i++) >> + dw_pcie_writeb_dbi(pci, cap + lane_eq_offset + i, presets[i]); >> +} >> + >> +static void dw_pcie_config_presets(struct dw_pcie_rp *pp) >> +{ >> + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); >> + enum pci_bus_speed speed = pcie_link_speed[pci->max_link_speed]; >> + >> + /* >> + * Lane equalization needs to be perfomed for all data rates >> + * the controller supports and for all supported lanes. >> + */ >> + >> + if (speed >= PCIE_SPEED_8_0GT) >> + dw_pcie_program_presets(pp, PCIE_SPEED_8_0GT); >> + >> + if (speed >= PCIE_SPEED_16_0GT) >> + dw_pcie_program_presets(pp, PCIE_SPEED_16_0GT); > > Add other data rates also. > > - Mani >