From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from szxga08-in.huawei.com (szxga08-in.huawei.com [45.249.212.255]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 06CF6194120 for ; Fri, 8 Nov 2024 08:06:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.255 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731053219; cv=none; b=m/BtG6UmX8dVzKwiYjMva34AtH/qT3k6SQBrMnjuoTVqr28HWv9l7q49XdXLntbtfI+wJrjyGVJB0P/HwqljkldfOtLEx5jveACDLjMwIkCuNKaf177mQAMNqmXf0G19zL+uAFTlBpEvy63poUVnHx5wZ3d5kIXHcJ0YA6qv6ys= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731053219; c=relaxed/simple; bh=oBX1fEbI/gFLZ8z5skbzdtXu5qGKGJQ9jpsmYNfHq5k=; h=CC:Subject:To:References:From:Message-ID:Date:MIME-Version: In-Reply-To:Content-Type; b=dS8i82WHKPGZ74p0H+xuaOuq3YshZRNvToGzXDnoKM4k+oMHskTxRvO8+kXw3M19C8sw0ElSYgyML2sNaiHzE64/D8kt5wypzPAvWzSyK5KdfsEzBf42s5p433utn4xvGsbbhXS8nb/nO5DaEEa/N7KkGyzda3x5JJU28k5FSTY= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=45.249.212.255 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.19.163.252]) by szxga08-in.huawei.com (SkyGuard) with ESMTP id 4XlBL52N1bz1T9sv; Fri, 8 Nov 2024 16:04:29 +0800 (CST) Received: from kwepemd200014.china.huawei.com (unknown [7.221.188.8]) by mail.maildlp.com (Postfix) with ESMTPS id BB09B1800D9; Fri, 8 Nov 2024 16:06:51 +0800 (CST) Received: from [10.67.121.177] (10.67.121.177) by kwepemd200014.china.huawei.com (7.221.188.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.34; Fri, 8 Nov 2024 16:06:50 +0800 CC: , , , , , , , , , , , , , , , , , , , , , , , Subject: Re: [PATCH v7 3/4] arm64: topology: Support SMT control on ACPI based system To: Pierre Gondois References: <20241030125415.18994-1-yangyicong@huawei.com> <20241030125415.18994-4-yangyicong@huawei.com> <63792865-46ad-44a5-a1f2-9a17da5b4bfc@arm.com> From: Yicong Yang Message-ID: <93a8b799-dfd9-5ffa-37ca-e7cd4a82e70e@huawei.com> Date: Fri, 8 Nov 2024 16:06:50 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.5.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 In-Reply-To: <63792865-46ad-44a5-a1f2-9a17da5b4bfc@arm.com> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit X-ClientProxiedBy: dggems701-chm.china.huawei.com (10.3.19.178) To kwepemd200014.china.huawei.com (7.221.188.8) On 2024/11/8 1:20, Pierre Gondois wrote: > > > On 10/30/24 13:54, Yicong Yang wrote: >> From: Yicong Yang >> >> For ACPI we'll build the topology from PPTT and we cannot directly >> get the SMT number of each core. Instead using a temporary xarray >> to record the heterogeneous information (from ACPI_PPTT_ACPI_IDENTICAL) >> and SMT information of the first core in its heterogeneous CPU cluster >> when building the topology. Then we can know the largest SMT number >> in the system. If a homogeneous system's using ACPI 6.2 or later, >> all the CPUs should be under the root node of PPTT. There'll be >> only one entry in the xarray and all the CPUs in the system will >> be assumed identical. >> >> The core's SMT control provides two interface to the users [1]: >> 1) enable/disable SMT by writing on/off >> 2) enable/disable SMT by writing thread number 1/max_thread_number >> >> If a system have more than one SMT thread number the 2) may >> not handle it well, since there're multiple thread numbers in the >> system and 2) only accept 1/max_thread_number. So issue a warning >> to notify the users if such system detected. >> >> [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/ABI/testing/sysfs-devices-system-cpu#n542 >> Signed-off-by: Yicong Yang >> --- >>   arch/arm64/kernel/topology.c | 57 ++++++++++++++++++++++++++++++++++++ >>   1 file changed, 57 insertions(+) >> [...] >> @@ -67,6 +106,24 @@ int __init parse_acpi_topology(void) >>           cpu_topology[cpu].package_id = topology_id; >>       } >>   +    /* >> +     * This should be a short loop depending on the number of heterogeneous >> +     * CPU clusters. Typically on a homogeneous system there's only one >> +     * entry in the XArray. >> +     */ >> +    xa_for_each(&hetero_cpu, hetero_id, entry) { >> +        if (entry->thread_num != max_smt_thread_num && max_smt_thread_num) >> +            pr_warn_once("Heterogeneous SMT topology is partly supported by SMT control\n"); >> + >> +        if (entry->thread_num > max_smt_thread_num) >> +            max_smt_thread_num = entry->thread_num; >> + >> +        xa_erase(&hetero_cpu, hetero_id); >> +        kfree(entry); >> +    } > > I think you need to check that max_smt_thread_num !=0, > like in the DT path. Otherwise on a platform with no SMT, > max_smt_thread_num = 0 and I hit: > > kernel/cpu::cpu_smt_set_num_threads() > WARN_ON(!num_threads || (num_threads > max_threads)); > > > -> > if (max_smt_thread_num) >     cpu_smt_set_num_threads(max_smt_thread_num, max_smt_thread_num); > sorry for this silly mistake. yes we should do the same like in the DT path. I'll get this fixed. thanks for testing. >> + >> +    cpu_smt_set_num_threads(max_smt_thread_num, max_smt_thread_num); >> +    xa_destroy(&hetero_cpu); >>       return 0; >>   } >>   #endif > > .