public inbox for linux-kernel@vger.kernel.org
 help / color / mirror / Atom feed
* RE: Intel vs AMD x86-64
@ 2004-02-24 21:01 Sean Fao
  2004-02-24 21:26 ` Linus Torvalds
  2004-02-24 21:31 ` Timothy Miller
  0 siblings, 2 replies; 78+ messages in thread
From: Sean Fao @ 2004-02-24 21:01 UTC (permalink / raw)
  To: Linus Torvalds; +Cc: linux-kernel

Linus Torvalds wrote:

>Now, I'm not above complaining about Intel (in fact, the Intel people seem
>to often think I hate them because I'm apparently the only person who gets
>quoted who complains about bad decisions publicly), but at least I try to
>avoid complaining before-the-fact ;)
>

It must come with the territory ;-).  Your message has already made it to
Slashdot so I'm sure this time will be no different.

^ permalink raw reply	[flat|nested] 78+ messages in thread
* RE: Intel vs AMD x86-64
@ 2004-03-02 23:22 Nakajima, Jun
  0 siblings, 0 replies; 78+ messages in thread
From: Nakajima, Jun @ 2004-03-02 23:22 UTC (permalink / raw)
  To: Kernel Mailing List

>-----Original Message-----
>From: Nakajima, Jun
>Sent: Tuesday, February 24, 2004 3:15 PM
>To: 'Pavel Machek'
>Cc: Linus Torvalds; Adrian Bunk; Herbert Poetzl; Mikael Pettersson;
Kernel
>Mailing List
>Subject: RE: Intel vs AMD x86-64
...
>Other than the standard IA-32 differences (eg. HT, SSE3, Intel Enhanced
>SpeedStep, etc.), there are few differences between the implementations
of
>IA-32e and AMD64. The software visible ones are:

Clarification to the BSF/BSR behavior when source is 0.

IA-32e inherits the existing behavior, which is "if the contents source
operand are 0, the contents of the destination operand is undefined."
One needs to check the ZF to detect such a condition. The defined
behavior for 64-bit mode is consistent with the one for 32-bit mode,
i.e. if the operand size is 64-bit, the whole destination is undefined
if the contents source operand are 0.

>BSF/BSR when source is 0 & operand size is 32:
>  In 64-bit mode, the processor sets ZF, and the upper 32 bits of
>  the destination are undefined. Should always check the ZF or do not
use
>  32-bit operand size.
>

So in this case, the lower 32 bits of the destination are undefined as
well, thus, the whole destination is undefined.

The advice is: Always check the ZF. You can use BSF/BSR with the 32-bit
operand size as long as you check the ZF. 

Jun


^ permalink raw reply	[flat|nested] 78+ messages in thread
* RE: Intel vs AMD x86-64
@ 2004-02-26  1:19 Nakajima, Jun
  2004-02-26 16:04 ` Timothy Miller
  0 siblings, 1 reply; 78+ messages in thread
From: Nakajima, Jun @ 2004-02-26  1:19 UTC (permalink / raw)
  To: H. Peter Anvin, Timothy Miller; +Cc: linux-kernel

Yes, that's the very reason I said "useless for compilers." The way
IP/RIP is updated is different (and implementation specific) on those
processors if 66H is used with a near branch. For example, RIP may be
zero-extended to 64 bits (from IP), as you observed before.

Jun
>-----Original Message-----
>From: H. Peter Anvin [mailto:hpa@zytor.com]
>Sent: Wednesday, February 25, 2004 4:14 PM
>To: Timothy Miller
>Cc: Nakajima, Jun; linux-kernel@vger.kernel.org
>Subject: Re: Intel vs AMD x86-64
>
>Timothy Miller wrote:
>>
>>
>> Nakajima, Jun wrote:
>>
>>> For near branches (CALL, RET, JCC, JCXZ, JMP, etc.), the operand
size is
>>> forced to 64 bits on both processors in 64-bit mode, basically
meaning
>>> RIP is updated.
>>>
>>> Compilers would typically use a JMP short for "intraprocedural
jumps",
>>> which requires just an 8-bit displacement relative to RIP.
>>
>> I see.  It's too bad you can't have a 16-bit displacement.
>>
>> Ummm... so if 66H were used with a near branch, would that affect the
>> size of the immediate operand which gets added to RIP, or would that
>> affect the the portion of IP/EIP/RIP affected?  If it's the latter,
>> that's pretty silly.
>>
>
>Yes, that would be pretty silly.
>
>I honestly don't remember off the top of my head what "o16 jmp blah"
>does on i386; I have a vague memory that it zero-extends %eip to 32
>bits, which makes it useless, of course.
>
>	-hpa


^ permalink raw reply	[flat|nested] 78+ messages in thread
* RE:  Re: Intel vs AMD x86-64
@ 2004-02-25 20:07 Nakajima, Jun
  2004-02-25 23:44 ` Timothy Miller
  0 siblings, 1 reply; 78+ messages in thread
From: Nakajima, Jun @ 2004-02-25 20:07 UTC (permalink / raw)
  To: H. Peter Anvin, linux-kernel

For near branches (CALL, RET, JCC, JCXZ, JMP, etc.), the operand size is
forced to 64 bits on both processors in 64-bit mode, basically meaning
RIP is updated.

Compilers would typically use a JMP short for "intraprocedural jumps",
which requires just an 8-bit displacement relative to RIP. 

Jun
>-----Original Message-----
>From: linux-kernel-owner@vger.kernel.org [mailto:linux-kernel-
>owner@vger.kernel.org] On Behalf Of H. Peter Anvin
>Sent: Wednesday, February 25, 2004 8:17 AM
>To: linux-kernel@vger.kernel.org
>Subject: Re: Intel vs AMD x86-64
>
>Followup to:  <403CCBE0.7050100@techsource.com>
>By author:    Timothy Miller <miller@techsource.com>
>In newsgroup: linux.dev.kernel
>>
>>
>> Nakajima, Jun wrote:
>> > No, it's not a problem. Branches with 16-bit operand size are not
>useful
>> > for compilers.
>>
>>  From AMD's documentation, I got the impression that 66H caused near
>> branches to be 32 bits in long mode (default is 64).
>>
>> So, Intel makes it 16 bits, and AMD makes it 32 bits?
>>
>> Either way, I don't see much use for either one.
>>
>
>Both claims are pretty bogus.  Shorter branches are quite nice for
>intraprocedural jumps; it reduces the cache footprint.
>
>	-hpa
>
>-
>To unsubscribe from this list: send the line "unsubscribe linux-kernel"
in
>the body of a message to majordomo@vger.kernel.org
>More majordomo info at  http://vger.kernel.org/majordomo-info.html
>Please read the FAQ at  http://www.tux.org/lkml/

^ permalink raw reply	[flat|nested] 78+ messages in thread
[parent not found: <1sRYA-1uZ-23@gated-at.bofh.it>]
* RE: Intel vs AMD x86-64
@ 2004-02-25  3:24 Nakajima, Jun
  2004-02-25 16:22 ` Timothy Miller
  0 siblings, 1 reply; 78+ messages in thread
From: Nakajima, Jun @ 2004-02-25  3:24 UTC (permalink / raw)
  To: Chris Wedgwood
  Cc: Pavel Machek, Linus Torvalds, Adrian Bunk, Herbert Poetzl,
	Mikael Pettersson, Kernel Mailing List

No, it's not a problem. Branches with 16-bit operand size are not useful
for compilers.

Jun 
>-----Original Message-----
>From: Chris Wedgwood [mailto:cw@f00f.org]
>Sent: Tuesday, February 24, 2004 5:53 PM
>To: Nakajima, Jun
>Cc: Pavel Machek; Linus Torvalds; Adrian Bunk; Herbert Poetzl; Mikael
>Pettersson; Kernel Mailing List
>Subject: Re: Intel vs AMD x86-64
>
>On Tue, Feb 24, 2004 at 03:15:18PM -0800, Nakajima, Jun wrote:
>
>> Near branch with 66H prefix:
>>   As documented in PRM the behavior is implementation specific and
>>   should avoid using 66H prefix on near branches.
>
>Presumably this isn't a problem with current gcc's right?
>


^ permalink raw reply	[flat|nested] 78+ messages in thread
* RE: Intel vs AMD x86-64
@ 2004-02-25  3:07 Nakajima, Jun
  0 siblings, 0 replies; 78+ messages in thread
From: Nakajima, Jun @ 2004-02-25  3:07 UTC (permalink / raw)
  To: ak; +Cc: linux-kernel

I think we have a bug in the inline function. Actually this behavior is 
consistent with the IA-32, which says "if the contents source operand
are 0, 
the contents of the destination operand is undefined." So the code in
32-bit 
also has a bug there. Today it is set to zero fortunately, and the code 
happens to be working.

Jun

>-----Original Message-----
>From: ak@suse.de [mailto:ak@suse.de]
>Sent: Tuesday, February 24, 2004 3:49 PM
>To: Nakajima, Jun
>Cc: linux-kernel@vger.kernel.org
>Subject: Re: Intel vs AMD x86-64
>
>"Nakajima, Jun" <jun.nakajima@intel.com> writes:
>
>> Other than the standard IA-32 differences (eg. HT, SSE3, Intel
Enhanced
>> SpeedStep, etc.), there are few differences between the
implementations
>> of
>> IA-32e and AMD64. The software visible ones are:
>
>Thanks for the detailed list.
>
>> BSF/BSR when source is 0 & operand size is 32:
>>   In 64-bit mode, the processor sets ZF, and the upper 32 bits of
>>   the destination are undefined. Should always check the ZF or do not
>> use
>>   32-bit operand size.
>
>This one sounds a bit scary. I think it could hurt the
>asm-x86_64/bitops.h:find_first_zero_bit if there is a race that
>changes the value in memory between the last scasl and the bsfl
>and the inliner assumes the edx output argument is zero extended.
>Hopefully that case should be unlikely enough. I guess best would
>be to change the function to use 64bit accesses to avoid this
completely.
>
>-Andi

^ permalink raw reply	[flat|nested] 78+ messages in thread
[parent not found: <7F740D512C7C1046AB53446D37200173EA2684@scsmsx402.sc.intel.com.suse.lists.linux.kernel>]
* RE: Intel vs AMD x86-64
@ 2004-02-24 23:15 Nakajima, Jun
  2004-02-25  1:52 ` Chris Wedgwood
  0 siblings, 1 reply; 78+ messages in thread
From: Nakajima, Jun @ 2004-02-24 23:15 UTC (permalink / raw)
  To: Pavel Machek
  Cc: Linus Torvalds, Adrian Bunk, Herbert Poetzl, Mikael Pettersson,
	Kernel Mailing List

>Could you publish list of differences between amd64 and ia32e?
>
>I probably could took those two 300+ page documents and try to compare
>them by hand, but I believe you know already.
>								
>								Pavel

Other than the standard IA-32 differences (eg. HT, SSE3, Intel Enhanced
SpeedStep, etc.), there are few differences between the implementations
of 
IA-32e and AMD64. The software visible ones are:

Fast system calls:
  Syscall/sysret is supported only in 64-bit mode (not in compatibility 
  mode). Sysenter/Sysexit is supported in both 64-bit and compatible
mode.

CPUID:
  If you look at Table 2-8 of Volume 1, you will find IA-32e specific
things,
  including, GenuineIntel, HT, SSE3, monitor/mwait, Intel Enhanced
SpeedStep, 
  and cmpxchg16b.

  The function 8000_0001h doesn't duplicate standard-feature bits from 
  function 1 in EDX. It sets only the new features that are implemented.

MSRs:
  Not all MSRs are architectural, and IA-32e does not implement SYSCFG, 
  TOP_MEM, TOP_MEM2, for example. MSR usage should be vendor specific
and 
  be guarded with CPUID.Model

Fast-FXSAVE/FXRSTOR:
  IA-32e always saves all of the FP state on FXSAVE/FXRSTOR. Does not 
  support FXSAVE/FXRSTOR with reduced FP state.

Microcode Update:
  IA-32e supports microcode update as the 32-bit mode does, as you
already 
  found the discussions in the mailing list.

NX (No-Execute) bit:
  Initial implementation will not support the NX bit.

BSF/BSR when source is 0 & operand size is 32:
  In 64-bit mode, the processor sets ZF, and the upper 32 bits of 
  the destination are undefined. Should always check the ZF or do not
use 
  32-bit operand size.

Near branch with 66H prefix:
  As documented in PRM the behavior is implementation specific and
should 
  avoid using 66H prefix on near branches.

Not supported in IA-32e
=======================
  3DNow instructions (including prefecthw or prefetch with the opcode 0f
0d)

Thanks,
Jun

>-----Original Message-----
>From: Pavel Machek [mailto:pavel@ucw.cz]
>Sent: Tuesday, February 24, 2004 5:25 AM
>To: Nakajima, Jun
>Cc: Linus Torvalds; Adrian Bunk; Herbert Poetzl; Mikael Pettersson;
Kernel
>Mailing List
>Subject: Re: Intel vs AMD x86-64
>
>Hi!
>
>> Sorry for the miscommunication. The page
>> http://www.intel.com/technology/64bitextensions/faq.htm says at the
>> _bottom_ at least:
>>
>> Q9: Is it possible to write software that will run on Intel's
processors
>> with 64-bit extension technology, and AMD's 64-bit capable
processors?
>> A9: With both companies designing entirely different architectures,
the
>> question is whether the operating system and software ported to each
>> processor will run on the other processor, and the answer is yes in
most
>> cases.
>
>Could you publish list of differences between amd64 and ia32e?
>
>I probably could took those two 300+ page documents and try to compare
>them by hand, but I believe you know already.
>								Pavel
>
>--
>When do you have a heart between your knees?
>[Johanka's followup: and *two* hearts?]

^ permalink raw reply	[flat|nested] 78+ messages in thread
* Re: Intel vs AMD x86-64
@ 2004-02-24  2:42 Albert Cahalan
  2004-02-24 16:44 ` Dave Jones
  0 siblings, 1 reply; 78+ messages in thread
From: Albert Cahalan @ 2004-02-24  2:42 UTC (permalink / raw)
  To: linux-kernel mailing list; +Cc: davem, Linus Torvalds

David S. Miller writes:
> Linus Torvalds <torvalds@osdl.org> wrote:

>> In fact, I _think_ you could actually use the AGP bridge as a strange
>> IOMMU. Of course, right now their AGP bridges are all 32-bit limited
>> anyway, but the point being that they at least in theory would seem to
>> have the capability to do this.
>
> Ok, I see.  In fact, I remember some vague notion that the AGP bridge
> on the Athlon's could technically be used as a full-on IOMMU, especially
> since it was all derived from Alpha PCI chipsets which did use things
> this way.

This is exactly the way it works. The AGP bridge is
a replicated per-CPU thing, along with the memory.
Good boards have a BIOS option marked "Linux only"
that lets you choose an IO-MMU window size ranging
from 32 MB to 2 GB. Direct your 32-bit PCI DMA
into that window and you get an IO-MMU.

Memory can be interleaved across the CPUs or not,
on 4 kB boundries. It's a BIOS option, though some
insane code could be written to change the setting.
Setting up only one of the IO-MMUs would be neat.




^ permalink raw reply	[flat|nested] 78+ messages in thread
* Re: Intel vs AMD x86-64
@ 2004-02-23 19:59 Xose Vazquez Perez
  0 siblings, 0 replies; 78+ messages in thread
From: Xose Vazquez Perez @ 2004-02-23 19:59 UTC (permalink / raw)
  To: linux-kernel

Adrian Bunk wrote:

> In the long term, x86_64 creates more confusion:
> - SuSE says AMD64 [1]
> - RedHat says AMD64 [2]
> - Debian says AMD64 [3]

AMD64 is the incarnation done by AMD and
IA-32e is the incarnation done by Intel
of x86-64 architecture.

I like x86-64 as a generic name, because the same kernel
port runs on both chips and they run the same binaries.

--
x86-64 GenuineIntel


^ permalink raw reply	[flat|nested] 78+ messages in thread
* RE: Intel vs AMD x86-64
@ 2004-02-23 18:10 Nakajima, Jun
  2004-02-24 13:25 ` Pavel Machek
  0 siblings, 1 reply; 78+ messages in thread
From: Nakajima, Jun @ 2004-02-23 18:10 UTC (permalink / raw)
  To: Linus Torvalds, Adrian Bunk
  Cc: Herbert Poetzl, Mikael Pettersson, Kernel Mailing List

Sorry for the miscommunication. The page
http://www.intel.com/technology/64bitextensions/faq.htm says at the
_bottom_ at least:

Q9: Is it possible to write software that will run on Intel's processors
with 64-bit extension technology, and AMD's 64-bit capable processors?
A9: With both companies designing entirely different architectures, the
question is whether the operating system and software ported to each
processor will run on the other processor, and the answer is yes in most
cases.

Jun

>-----Original Message-----
>From: linux-kernel-owner@vger.kernel.org [mailto:linux-kernel-
>owner@vger.kernel.org] On Behalf Of Linus Torvalds
>Sent: Monday, February 23, 2004 9:31 AM
>To: Adrian Bunk
>Cc: Herbert Poetzl; Mikael Pettersson; Kernel Mailing List
>Subject: Re: Intel vs AMD x86-64
>
>
>
>On Mon, 23 Feb 2004, Adrian Bunk wrote:
>>
>> In the long term, x86_64 creates more confusion:
>> - SuSE says AMD64 [1]
>> - RedHat says AMD64 [2]
>> - Debian says AMD64 [3]
>>
>> Renaming might be some work today, but it might actually remove
>> confusion in the future.
>
>Well, the thing is, I _like_ a vendor-neutral name.
>
>I think it's important to have multiple sources for a chip, and I think
>one of the problems with IA-64 was that it was a locked-in chip with
>patents and no serious competition internally (ignore the Intel
mouthing
>about "open").
>
>The x86 is so great partly because there's been real competition. So I
>think it's very important to x86-64 to have real competition to make
sure
>nobody gets too dishonest.
>
>So AMD64 is a bad name, partly for the same reason IA32 is a horrible
name
>(and who have you ever heard use the IA32 name except for people who
are
>paid to do so by Intel?)
>
>What I found so irritating is that _hours_ after the Intel
announcement,
>people were _still_ confused about whether the new intel chip was
actually
>compatible with AMD's chips. Why the f*ck not just come out and say so,
>and talk about it? It took people actually reading the manuals (which
>didn't mention it either) to convince some people on the architecture
>newsgroups that yes, "ia32e" was really the same as "amd64" except in
the
>small details that have always set Intel and AMD apart.
>
>So I don't really want to change the name. "x86-64" is a good name. I
just
>wish there was more honesty involved, and less friggin *POSTURING*.
>
>			Linus
>-
>To unsubscribe from this list: send the line "unsubscribe linux-kernel"
in
>the body of a message to majordomo@vger.kernel.org
>More majordomo info at  http://vger.kernel.org/majordomo-info.html
>Please read the FAQ at  http://www.tux.org/lkml/

^ permalink raw reply	[flat|nested] 78+ messages in thread
* Re: Intel vs AMD x86-64
@ 2004-02-18 21:28 Peter Maas
  0 siblings, 0 replies; 78+ messages in thread
From: Peter Maas @ 2004-02-18 21:28 UTC (permalink / raw)
  To: linux-kernel

Hit send too soon...

INTEL HAS PUT up a 354 page PDF which describes software developing for the
64 bit extensions that will appear in the Nocona and Prescott processors.


> http://www.theinquirer.net/?article=14222
>
> ____________________________________________________________________
>
> Ok,
> now that Intel has finally come clean about their x86-64 implementation
> (see
>
>
http://www.intel.com/technology/64bitextensions/index.htm?iid=techtrends+spotlight_64bit
>
> for full details), can somebody write up a list of differences? I know
> there are people who have had access to the Intel docs for a while now,
> and obviously Intel is too frigging proud to list the differences
> explicitly.
>
> >From what I can tell from a quick look, it looks like it is basically
just
> the 3DNow vs SSE3 thing, but I assume there are other details too. Can
> people who have been involved with this make a quick list for the rest of
> us who only got to see the final details today?
>
> (And I assume there's somebody with a few patches pending..)
>
> Thanks,
> Linus
> -
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
> the body of a message to majordomo@xxxxxxxxxxxxxxx
> More majordomo info at http://vger.kernel.org/majordomo-info.html
> Please read the FAQ at http://www.tux.org/lkml/
>


^ permalink raw reply	[flat|nested] 78+ messages in thread
* Re: Intel vs AMD x86-64
@ 2004-02-18 21:26 Peter Maas
  0 siblings, 0 replies; 78+ messages in thread
From: Peter Maas @ 2004-02-18 21:26 UTC (permalink / raw)
  To: linux-kernel

http://www.theinquirer.net/?article=14222

____________________________________________________________________

Ok,
now that Intel has finally come clean about their x86-64 implementation
(see

http://www.intel.com/technology/64bitextensions/index.htm?iid=techtrends+spotlight_64bit

for full details), can somebody write up a list of differences? I know
there are people who have had access to the Intel docs for a while now,
and obviously Intel is too frigging proud to list the differences
explicitly.

>From what I can tell from a quick look, it looks like it is basically just
the 3DNow vs SSE3 thing, but I assume there are other details too. Can
people who have been involved with this make a quick list for the rest of
us who only got to see the final details today?

(And I assume there's somebody with a few patches pending..)

Thanks,
Linus
-
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@xxxxxxxxxxxxxxx
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/


^ permalink raw reply	[flat|nested] 78+ messages in thread
* Intel vs AMD x86-64
@ 2004-02-18  1:44 Linus Torvalds
  2004-02-18  9:56 ` Mikael Pettersson
  2004-02-19  9:15 ` Terje Eggestad
  0 siblings, 2 replies; 78+ messages in thread
From: Linus Torvalds @ 2004-02-18  1:44 UTC (permalink / raw)
  To: Kernel Mailing List


Ok, 
 now that Intel has finally come clean about their x86-64 implementation
(see

	http://www.intel.com/technology/64bitextensions/index.htm?iid=techtrends+spotlight_64bit

for full details), can somebody write up a list of differences? I know
there are people who have had access to the Intel docs for a while now,
and obviously Intel is too frigging proud to list the differences
explicitly.

>From what I can tell from a quick look, it looks like it is basically just
the 3DNow vs SSE3 thing, but I assume there are other details too.  Can
people who have been involved with this make a quick list for the rest of
us who only got to see the final details today?

(And I assume there's somebody with a few patches pending..)

	Thanks,
		Linus

^ permalink raw reply	[flat|nested] 78+ messages in thread

end of thread, other threads:[~2004-03-02 23:22 UTC | newest]

Thread overview: 78+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2004-02-24 21:01 Intel vs AMD x86-64 Sean Fao
2004-02-24 21:26 ` Linus Torvalds
2004-02-24 22:21   ` Timothy Miller
2004-02-25 22:30   ` Davide Rossetti
2004-02-24 21:31 ` Timothy Miller
2004-02-24 21:31   ` Linus Torvalds
2004-02-24 21:28     ` Dave Jones
2004-02-26 21:39       ` Kai Henningsen
  -- strict thread matches above, loose matches on Subject: below --
2004-03-02 23:22 Nakajima, Jun
2004-02-26  1:19 Nakajima, Jun
2004-02-26 16:04 ` Timothy Miller
2004-02-27  3:16   ` Bill Davidsen
2004-02-25 20:07 Nakajima, Jun
2004-02-25 23:44 ` Timothy Miller
2004-02-26  0:13   ` H. Peter Anvin
     [not found] <1sRYA-1uZ-23@gated-at.bofh.it>
     [not found] ` <1sSi2-1NC-5@gated-at.bofh.it>
     [not found]   ` <1sT4l-2CW-17@gated-at.bofh.it>
2004-02-25 15:41     ` Bill Davidsen
2004-02-25 16:08       ` Moritz Muehlenhoff
2004-02-25  3:24 Nakajima, Jun
2004-02-25 16:22 ` Timothy Miller
2004-02-25 16:17   ` H. Peter Anvin
2004-02-25 17:18     ` Timothy Miller
2004-02-25 17:16       ` H. Peter Anvin
2004-02-25 19:05         ` Timothy Miller
2004-02-25  3:07 Nakajima, Jun
     [not found] <7F740D512C7C1046AB53446D37200173EA2684@scsmsx402.sc.intel.com.suse.lists.linux.kernel>
2004-02-24 23:49 ` Andi Kleen
2004-02-24 23:15 Nakajima, Jun
2004-02-25  1:52 ` Chris Wedgwood
2004-02-24  2:42 Albert Cahalan
2004-02-24 16:44 ` Dave Jones
2004-02-24 15:11   ` Albert Cahalan
2004-02-24 17:34     ` Dave Jones
2004-02-24 15:29       ` Albert Cahalan
2004-02-24 18:07         ` Dave Jones
2004-02-23 19:59 Xose Vazquez Perez
2004-02-23 18:10 Nakajima, Jun
2004-02-24 13:25 ` Pavel Machek
2004-02-18 21:28 Peter Maas
2004-02-18 21:26 Peter Maas
2004-02-18  1:44 Linus Torvalds
2004-02-18  9:56 ` Mikael Pettersson
2004-02-18 14:31   ` Diego Calleja García
2004-02-18 18:17     ` Bryan O'Sullivan
2004-02-18 14:54   ` Stefan Smietanowski
2004-02-18 15:47   ` Linus Torvalds
2004-02-22  2:59     ` Herbert Poetzl
2004-02-22  3:12       ` Linus Torvalds
2004-02-22  3:39         ` Tomasz Rola
2004-02-22  3:47           ` Mike Fedyk
2004-02-22  4:12         ` Scott Robert Ladd
2004-02-23  0:38           ` Timothy Miller
2004-02-23  2:17             ` Tom Vier
2004-02-22  8:38         ` Geert Uytterhoeven
2004-02-22 10:00         ` Vojtech Pavlik
2004-02-23 15:51         ` Clay Haapala
2004-02-23 17:03         ` Adrian Bunk
2004-02-23 17:31           ` Linus Torvalds
2004-02-24  9:47             ` Kees Bakker
2004-02-24  9:59               ` viro
2004-02-24 10:59             ` Andrew Walrond
2004-02-23 18:56           ` Christoph Hellwig
2004-02-23 21:25         ` Rik van Riel
2004-02-23 21:36           ` Linus Torvalds
2004-02-23 21:48             ` David S. Miller
2004-02-23 22:08               ` Linus Torvalds
2004-02-23 22:06                 ` David S. Miller
2004-02-23 22:56             ` H. Peter Anvin
2004-02-24  1:01         ` Thomas Zehetbauer
2004-02-24  1:11           ` John Heil
2004-02-24 13:32             ` Timothy Miller
2004-02-24 14:39               ` Scott Robert Ladd
2004-02-24 19:43               ` Rogier Wolff
2004-02-24 19:49                 ` John Heil
2004-02-24 20:03                   ` Mike Fedyk
2004-02-24 20:03                     ` John Heil
2004-02-24 21:20                   ` Timothy Miller
2004-02-25 18:40         ` Matt Seitz
2004-02-18 19:13   ` Aaron Lehmann
2004-02-19  6:02     ` Mikael Pettersson
2004-02-19  9:15 ` Terje Eggestad

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox