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Mon, 7 Jul 2025 11:12:34 -0700 (PDT) Message-ID: <94d2de81-47e4-4ad1-ab92-cfacdab3cf68@linux.intel.com> Date: Mon, 7 Jul 2025 11:12:32 -0700 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC PATCH V2 06/13] perf: Support SIMD registers To: Mark Brown Cc: peterz@infradead.org, mingo@redhat.com, acme@kernel.org, namhyung@kernel.org, tglx@linutronix.de, dave.hansen@linux.intel.com, irogers@google.com, adrian.hunter@intel.com, jolsa@kernel.org, alexander.shishkin@linux.intel.com, linux-kernel@vger.kernel.org, dapeng1.mi@linux.intel.com, ak@linux.intel.com, zide.chen@intel.com, mark.rutland@arm.com, ravi.bangoria@amd.com References: <20250626195610.405379-1-kan.liang@linux.intel.com> <20250626195610.405379-7-kan.liang@linux.intel.com> <69afb239-da54-452d-8ab4-2d80dbdf8dce@sirena.org.uk> Content-Language: en-US From: "Liang, Kan" In-Reply-To: <69afb239-da54-452d-8ab4-2d80dbdf8dce@sirena.org.uk> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 2025-07-02 4:16 a.m., Mark Brown wrote: > On Thu, Jun 26, 2025 at 12:56:03PM -0700, kan.liang@linux.intel.com wrote: > >> * { u64 abi; # enum perf_sample_regs_abi >> - * u64 regs[weight(mask)]; } && PERF_SAMPLE_REGS_USER >> + * u64 regs[weight(mask)]; >> + * struct { >> + * u16 nr_vectors; >> + * u16 vector_qwords; >> + * u16 nr_pred; >> + * u16 pred_qwords; >> + * u64 data[nr_vectors * vector_qwords + nr_pred * pred_qwords]; >> + * } && (abi & PERF_SAMPLE_REGS_ABI_SIMD) >> + * } && PERF_SAMPLE_REGS_USER > > I'm not super familiar with perf but I think this should work for arm64, > it supplies the vector length through the _qwords and we can handle FFR > being optional by varying the number of predicate registers. That's great. Thanks for the confirmation. Thanks, Kan