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X-CSE-ConnectionGUID: x1TfWolVSAawgUdZFDMxog== X-CSE-MsgGUID: tcZFM1eVQeaex68+sPwvGQ== X-IronPort-AV: E=McAfee;i="6800,10657,11563"; a="60822892" X-IronPort-AV: E=Sophos;i="6.18,292,1751266800"; d="scan'208";a="60822892" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Sep 2025 06:23:15 -0700 X-CSE-ConnectionGUID: 61lDqMiaSL6gENqN3DozbA== X-CSE-MsgGUID: k8SaqhLvQp6Ar1H+hx1rFA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.18,292,1751266800"; d="scan'208";a="177169144" Received: from mylly.fi.intel.com (HELO [10.237.72.50]) ([10.237.72.50]) by orviesa007.jf.intel.com with ESMTP; 25 Sep 2025 06:23:12 -0700 Message-ID: <9708c09f-5cd7-4197-b245-04d92f6b1400@linux.intel.com> Date: Thu, 25 Sep 2025 16:23:10 +0300 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/4] i3c: mipi-i3c-hci: add microchip sama7d65 SoC To: Frank Li , Durai Manickam KR Cc: linux-i3c@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, alexandre.belloni@bootlin.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, balamanikandan.gunasundar@microchip.com, nicolas.ferre@microchip.com References: <20250918095429.232710-1-durai.manickamkr@microchip.com> <20250918095429.232710-3-durai.manickamkr@microchip.com> Content-Language: en-US From: Jarkko Nikula In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Hi On 9/18/25 7:27 PM, Frank Li wrote: > On Thu, Sep 18, 2025 at 03:24:27PM +0530, Durai Manickam KR wrote: >> Add support for microchip sama7d65 SoC I3C HCI master only IP. >> Features tested and supported : >> Standard CCC commands. >> I3C SDR mode private transfers in PIO mode. >> I2C transfers in PIO mode. >> Pure bus mode and mixed bus mode. >> >> Signed-off-by: Durai Manickam KR >> --- >> drivers/i3c/master/mipi-i3c-hci/Makefile | 3 +- >> drivers/i3c/master/mipi-i3c-hci/core.c | 28 ++++++++++++ >> drivers/i3c/master/mipi-i3c-hci/hci.h | 12 ++++++ >> .../i3c/master/mipi-i3c-hci/hci_quirks_mchp.c | 43 +++++++++++++++++++ >> 4 files changed, 85 insertions(+), 1 deletion(-) >> create mode 100644 drivers/i3c/master/mipi-i3c-hci/hci_quirks_mchp.c >> >> diff --git a/drivers/i3c/master/mipi-i3c-hci/Makefile b/drivers/i3c/master/mipi-i3c-hci/Makefile >> index e3d3ef757035..f463afc4566a 100644 >> --- a/drivers/i3c/master/mipi-i3c-hci/Makefile >> +++ b/drivers/i3c/master/mipi-i3c-hci/Makefile >> @@ -4,5 +4,6 @@ obj-$(CONFIG_MIPI_I3C_HCI) += mipi-i3c-hci.o >> mipi-i3c-hci-y := core.o ext_caps.o pio.o dma.o \ >> cmd_v1.o cmd_v2.o \ >> dat_v1.o dct_v1.o \ >> - hci_quirks.o >> + hci_quirks.o \ >> + hci_quirks_mchp.o >> obj-$(CONFIG_MIPI_I3C_HCI_PCI) += mipi-i3c-hci-pci.o >> diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mipi-i3c-hci/core.c >> index 60f1175f1f37..cb0673d62c03 100644 >> --- a/drivers/i3c/master/mipi-i3c-hci/core.c >> +++ b/drivers/i3c/master/mipi-i3c-hci/core.c >> @@ -8,6 +8,7 @@ >> */ >> >> #include >> +#include >> #include >> #include >> #include >> @@ -651,6 +652,9 @@ static int i3c_hci_init(struct i3c_hci *hci) >> hci->DAT_regs = offset ? hci->base_regs + offset : NULL; >> hci->DAT_entries = FIELD_GET(DAT_TABLE_SIZE, regval); >> hci->DAT_entry_size = FIELD_GET(DAT_ENTRY_SIZE, regval) ? 0 : 8; >> + /* Microchip SAMA7D65 SoC doesnot support DAT entry size bits in the DAT section offset register */ >> + if (hci->quirks & MCHP_HCI_QUIRK_SAMA7D65) >> + hci->DAT_entry_size = 8; > > #define MCHP_HCI_QUIRK_FIX_DATA_ENTRY_SIZE_8 > > if (hci->quirks & MCHP_HCI_QUIRK_FIX_DATA_ENTRY_SIZE_8) > hci->DAT_entry_size = 8; > else > hci->DAT_entry_size = FIELD_GET(DAT_ENTRY_SIZE, regval) ? 0 : 8; > > in case other vendor have similar problem. > Are DAT_entry_size and DCT_entry_size quirks even needed? Does your HW read nonzero values and you need the quirk? >> + /* Microchip SAMA7d65 SoC supports only PIO mode */ >> + if (hci->quirks & MCHP_HCI_QUIRK_PIO_MODE) >> + hci->RHS_regs = NULL; >> + Please use existing HCI_QUIRK_PIO_MODE quirk and then you don't need this added code.