From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4276F2DC76E for ; Tue, 25 Nov 2025 08:38:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.21 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764059892; cv=none; b=gLoPuqQbb+Z0PQqEFMeT64w8K7fLIkfLZRpIYW7Wzx3tvNP7bDesZzT5EEEVbQLDS5N7h6tkwzXt6EqyZhoSLwa9kFD/MCufjy99N1ZCC1jI5F7ERB5RZ7xIqYMfZpreU2iKNwnpMLrhNXJafHFRYj4TFKqmeiqBt8fmA2NL8h0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764059892; c=relaxed/simple; bh=4hPbvwObn922jRZBV2FDZK1+G0Cd3qDpcAe+yyEEais=; h=From:To:Subject:In-Reply-To:References:Date:Message-ID: MIME-Version:Content-Type; b=UGRVpBHR/TkSGE2pkuHu7xCvvoRfg3rC7FXbJiBYLqG6DtDDGRitKLczlJADG3qBfRwdfqCmku+CEfpzZO+qC7uJG1pa0/HD8X7X8yyVvqoPqy/8YIIypexoeBALuOjfhYICLmv+nxNrFpueQsWn0J0EDn4ALYzHh6UxJqlSetc= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=W1CeM/U4; arc=none smtp.client-ip=198.175.65.21 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="W1CeM/U4" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1764059891; x=1795595891; h=from:to:subject:in-reply-to:references:date:message-id: mime-version; bh=4hPbvwObn922jRZBV2FDZK1+G0Cd3qDpcAe+yyEEais=; b=W1CeM/U4VibBv3SnYQ+nVzFGxuNe5uBC5UXqyq7HeXFvfcldp5cykTmy v7RgW8+He2UsUdxFAQCToDfEXO33Fi7YAkkQ1BWO8pU161y7RDJfxA9+L E9rYYGqNCCDu4GmD4d91pvqW8XK8Pv/ropdL0bmoA/P3zof6PBe04HGfz nsD+CI4cfh9iiVDcZKPsvyPab3qiZEAu2LEwUDf4sHONQyYIcKW/H0sAq 03tfzm4FVAcY5RRtyRcZUjY0x++oFslrL/6birMAMHhYlJmXmoBee5T+T LWbyciMWcJih9wuMBeU1zdNqa1lxj51vayObSmn1oP7fKMwbW2FQ3Ra89 A==; X-CSE-ConnectionGUID: 7dIPT+LSRR+QxheoBDVHVQ== X-CSE-MsgGUID: +ro4RBvoRaG8ujHbqNYaqw== X-IronPort-AV: E=McAfee;i="6800,10657,11623"; a="66016465" X-IronPort-AV: E=Sophos;i="6.20,225,1758610800"; d="scan'208";a="66016465" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Nov 2025 00:38:10 -0800 X-CSE-ConnectionGUID: gbstitpnRhSiOx4K8cKupA== X-CSE-MsgGUID: ONNzabv0SdO53OtAwTJbow== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.20,225,1758610800"; d="scan'208";a="197689402" Received: from ettammin-desk.ger.corp.intel.com (HELO localhost) ([10.245.246.213]) by orviesa005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Nov 2025 00:38:04 -0800 From: Jani Nikula To: zhangzhijie , jeff@jeffgeerling.com, zhangzhijie@bosc.ac.cn, wangran@bosc.ac.cn, zhangjian@bosc.ac.cn, daniel@ffwll.ch, rodrigo.vivi@intel.com, joonas.lahtinen@linux.intel.com, tursulin@ursulin.net, airlied@gmail.com, intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, guoyaxing@bosc.ac.cn, ville.syrjala@linux.intel.com Subject: Re: [PATCH v2/2] i915: Support Intel GPU porting on any non-x86 system. In-Reply-To: <20251125033420.2265288-1-zhangzhijie@bosc.ac.cn> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo References: <20251125033420.2265288-1-zhangzhijie@bosc.ac.cn> Date: Tue, 25 Nov 2025 10:38:01 +0200 Message-ID: <98262d9d2ea7c02858aafae680a3ca0ff0a9dc9a@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain On Tue, 25 Nov 2025, zhangzhijie wrote: > inb/outb speccial wire not support on other ARCH. > Should detect whether arch platform support or not. I would rather finish the discussion on the previous version before seeing a new version. You mentioned risc-v in the previous thread, but it needs to be part of the commit message too. And I still don't know what "speccial wire" is supposed to mean here. You still use likely/unlikely, and I told you not to. There's no patch changelog. The version in the subject is "v2/2", but there has already been two "v2" posted previously. BR, Jani. > > Signed-off-by: zhangzhijie > --- > drivers/gpu/drm/i915/display/intel_vga.c | 33 +++++++++++++++++------- > 1 file changed, 23 insertions(+), 10 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_vga.c b/drivers/gpu/drm/i915/display/intel_vga.c > index 6e125564db34..d85622ba10fc 100644 > --- a/drivers/gpu/drm/i915/display/intel_vga.c > +++ b/drivers/gpu/drm/i915/display/intel_vga.c > @@ -41,6 +41,15 @@ static bool has_vga_pipe_sel(struct intel_display *display) > return DISPLAY_VER(display) < 7; > } > > +static bool intel_arch_support_vga_pm(struct intel_display *display) > +{ > +#if defined(CONFIG_X86) || defined(CONFIG_X86_64) > + return true; > +#else > + return false; > +#endif > +} > + > /* Disable the VGA plane that we never use */ > void intel_vga_disable(struct intel_display *display) > { > @@ -64,13 +73,15 @@ void intel_vga_disable(struct intel_display *display) > drm_dbg_kms(display->drm, "Disabling VGA plane on pipe %c\n", > pipe_name(pipe)); > > - /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ > - vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO); > - outb(0x01, VGA_SEQ_I); > - sr1 = inb(VGA_SEQ_D); > - outb(sr1 | VGA_SR01_SCREEN_OFF, VGA_SEQ_D); > - vga_put(pdev, VGA_RSRC_LEGACY_IO); > - udelay(300); > + if (likely(intel_arch_support_vga_pm(display))) { > + /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ > + vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO); > + outb(0x01, VGA_SEQ_I); > + sr1 = inb(VGA_SEQ_D); > + outb(sr1 | VGA_SR01_SCREEN_OFF, VGA_SEQ_D); > + vga_put(pdev, VGA_RSRC_LEGACY_IO); > + udelay(300); > + } > > intel_de_write(display, vga_reg, VGA_DISP_DISABLE); > intel_de_posting_read(display, vga_reg); > @@ -90,9 +101,11 @@ void intel_vga_reset_io_mem(struct intel_display *display) > * sure vgacon can keep working normally without triggering interrupts > * and error messages. > */ > - vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO); > - outb(inb(VGA_MIS_R), VGA_MIS_W); > - vga_put(pdev, VGA_RSRC_LEGACY_IO); > + if (likely(intel_arch_support_vga_pm(display))) { > + vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO); > + outb(inb(VGA_MIS_R), VGA_MIS_W); > + vga_put(pdev, VGA_RSRC_LEGACY_IO); > + } > } > > int intel_vga_register(struct intel_display *display) -- Jani Nikula, Intel