From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.3 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 65D2EC4BA06 for ; Wed, 26 Feb 2020 01:32:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 405E121744 for ; Wed, 26 Feb 2020 01:32:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729908AbgBZBch (ORCPT ); Tue, 25 Feb 2020 20:32:37 -0500 Received: from mga05.intel.com ([192.55.52.43]:9676 "EHLO mga05.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729395AbgBZBch (ORCPT ); Tue, 25 Feb 2020 20:32:37 -0500 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 25 Feb 2020 17:32:37 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,486,1574150400"; d="scan'208";a="241509135" Received: from linux.intel.com ([10.54.29.200]) by orsmga006.jf.intel.com with ESMTP; 25 Feb 2020 17:32:36 -0800 Received: from [10.226.38.18] (unknown [10.226.38.18]) by linux.intel.com (Postfix) with ESMTP id EE2A3580544; Tue, 25 Feb 2020 17:32:33 -0800 (PST) Subject: Re: [PATCH v10 1/2] dt-bindings: spi: Add schema for Cadence QSPI Controller driver To: Vignesh Raghavendra , Rob Herring Cc: "linux-kernel@vger.kernel.org" , linux-spi , Mark Brown , simon.k.r.goldschmidt@gmail.com, Dinh Nguyen , tien.fong.chee@intel.com, =?UTF-8?Q?Marek_Va=c5=a1ut?= , cheol.yong.kim@intel.com, qi-ming.wu@intel.com References: <20200219022852.28065-1-vadivel.muruganx.ramuthevar@linux.intel.com> <20200219022852.28065-2-vadivel.muruganx.ramuthevar@linux.intel.com> <64b7ab12-0c11-df25-95e7-ee62227ec7ec@linux.intel.com> <85178128-4906-8b1a-e3f1-ab7a36ff8c23@ti.com> <8c329860-84fd-463b-782f-83a788998878@ti.com> From: "Ramuthevar, Vadivel MuruganX" Message-ID: <98c90f35-297b-a13c-61ad-ce7a7f1d650f@linux.intel.com> Date: Wed, 26 Feb 2020 09:32:31 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.9.1 MIME-Version: 1.0 In-Reply-To: <8c329860-84fd-463b-782f-83a788998878@ti.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Content-Language: en-US Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On 25/2/2020 7:00 PM, Vignesh Raghavendra wrote: > > On 25/02/20 1:08 pm, Ramuthevar, Vadivel MuruganX wrote: >>>>>> + >>>>>> +  cdns,fifo-depth: >>>>>> +    $ref: /schemas/types.yaml#/definitions/uint32 >>>>>> +    description: >>>>>> +      Size of the data FIFO in words. >>>>> A 4GB fifo is valid? Add some constraints. >>>> 128 is valid, will update. >>> Nope, the width of this field is 8bits -> 256 bytes >> correct me if I am wrong, the width of this field is 4bits -> 128 bytes >> (based on QUAD mode) . > This has nothing to do with quad-mode. Its about how much SRAM amount of > SRAM is present to buffer INDAC mode data. For TI platforms this is 256 > bytes. > See CQSPI_REG_SRAMPARTITION definition in your datasheet. Agreed, Thanks! Yes , I have gone through it , Intel and Altera SoC's SRAM(act as FIFO)size is 128 bytes and TI has 256 . BTW old legacy DT binding mentioned size is 128, as per your earlier suggestion you have mention that keep the contents from old dt bindings as it is, so shall I keep 128/256? Regards Vadivel