Re: [PATCH v4 2/3] iio: frequency: adf4371: add refin mode

Nuno Sá
2025-01-13T09:59:44Z

On Mon, 2025-01-13 at 09:57 +0000, Nuno Sá wrote:
> On Thu, 2025-01-09 at 15:37 +0200, Antoniu Miclaus wrote:
> > Add support for single-ended/differential reference input mode.
> >
> > Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com>
> > ---
>
> Reviewed-by: Nuno Sa <nunbo.sa@analog.com>

Ups, typo:

Reviewed-by: Nuno Sa <nuno.sa@analog.com>

>
> > changes in v4:
> >  - parse input clock depending on the name and adjust the refin mode
> >    accordingly.
> >  drivers/iio/frequency/adf4371.c | 28 ++++++++++++++++++++++++++--
> >  1 file changed, 26 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/iio/frequency/adf4371.c
> > b/drivers/iio/frequency/adf4371.c
> > index b27088464826..50450e7b5464 100644
> > --- a/drivers/iio/frequency/adf4371.c
> > +++ b/drivers/iio/frequency/adf4371.c
> > @@ -41,6 +41,10 @@
> >  #define ADF4371_MOD2WORD_MSK GENMASK(5, 0)
> >  #define ADF4371_MOD2WORD(x) FIELD_PREP(ADF4371_MOD2WORD_MSK, x)
> >
> > +/* ADF4371_REG22 */
> > +#define ADF4371_REFIN_MODE_MASK BIT(6)
> > +#define ADF4371_REFIN_MODE(x) FIELD_PREP(ADF4371_REFIN_MODE_MASK,
> > x)
> > +
> >  /* ADF4371_REG24 */
> >  #define ADF4371_RF_DIV_SEL_MSK GENMASK(6, 4)
> >  #define ADF4371_RF_DIV_SEL(x) FIELD_PREP(ADF4371_RF_DIV_SEL_MSK,
> > x)
> > @@ -69,6 +73,7 @@
> >
> >  #define ADF4371_MAX_FREQ_PFD 250000000UL /* Hz */
> >  #define ADF4371_MAX_FREQ_REFIN 600000000UL /* Hz */
> > +#define ADF4371_MAX_FREQ_REFIN_SE 500000000UL /* Hz */
> >
> >  /* MOD1 is a 24-bit primary modulus with fixed value of 2^25 */
> >  #define ADF4371_MODULUS1 33554432ULL
> > @@ -175,6 +180,7 @@ struct adf4371_state {
> >   unsigned int mod2;
> >   unsigned int rf_div_sel;
> >   unsigned int ref_div_factor;
> > + bool ref_diff_en;
> >   u8 buf[10] __aligned(IIO_DMA_MINALIGN);
> >  };
> >
> > @@ -503,6 +509,17 @@ static int adf4371_setup(struct adf4371_state *st)
> >   ADF4371_ADDR_ASC(1) |
> > ADF4371_ADDR_ASC_R(1));
> >   if (ret < 0)
> >   return ret;
> > +
> > + if ((st->ref_diff_en && st->clkin_freq > ADF4371_MAX_FREQ_REFIN) ||
> > +     (!st->ref_diff_en && st->clkin_freq >
> > ADF4371_MAX_FREQ_REFIN_SE))
> > + return -EINVAL;
> > +
> > + ret = regmap_update_bits(st->regmap,  ADF4371_REG(0x22),
> > + ADF4371_REFIN_MODE_MASK,
> > + ADF4371_REFIN_MODE(st->ref_diff_en));
> > + if (ret < 0)
> > + return ret;
> > +
> >   /*
> >   * Calculate and maximize PFD frequency
> >   * fPFD = REFIN × ((1 + D)/(R × (1 + T)))
> > @@ -572,9 +589,16 @@ static int adf4371_probe(struct spi_device *spi)
> >   indio_dev->channels = st->chip_info->channels;
> >   indio_dev->num_channels = st->chip_info->num_channels;
> >
> > + st->ref_diff_en = false;
> > +
> >   st->clkin = devm_clk_get_enabled(&spi->dev, "clkin");
> > - if (IS_ERR(st->clkin))
> > - return PTR_ERR(st->clkin);
> > + if (IS_ERR(st->clkin)) {
> > + st->clkin = devm_clk_get_enabled(&spi->dev, "clkin-diff");
> > + if (IS_ERR(st->clkin))
> > + return PTR_ERR(st->clkin);
> > +
> > + st->ref_diff_en = true;
> > + }
> >
> >   st->clkin_freq = clk_get_rate(st->clkin);
> >
>