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In-Reply-To: <20241014-imx-clk-v1-v1-1-ee75876d3102@nxp.com>
References: <20241014-imx-clk-v1-v1-0-ee75876d3102@nxp.com> <20241014-imx-clk-v1-v1-1-ee75876d3102@nxp.com>
Subject: Re: [PATCH 1/4] clk: imx: lpcg-scu: SW workaround for errata (e10858)
From: Stephen Boyd <sboyd@kernel.org>
Cc: linux-clk@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Peng Fan <peng.fan@nxp.com>
To: Abel Vesa <abelvesa@kernel.org>, Aisheng Dong <aisheng.dong@nxp.com>, Fabio Estevam <festevam@gmail.com>, Michael Turquette <mturquette@baylibre.com>, Peng Fan (OSS) <peng.fan@oss.nxp.com>, Pengutronix Kernel Team <kernel@pengutronix.de>, Sascha Hauer <s.hauer@pengutronix.de>, Shawn Guo <shawnguo@kernel.org>
Date: Wed, 16 Oct 2024 14:46:42 -0700
User-Agent: alot/0.10

Quoting Peng Fan (OSS) (2024-10-14 02:11:22)
> diff --git a/drivers/clk/imx/clk-lpcg-scu.c b/drivers/clk/imx/clk-lpcg-sc=
u.c
> index dd5abd09f3e206a5073767561b517d5b3320b28c..2cffec0c42dccc256e8dc5e91=
81952e250870a76 100644
> --- a/drivers/clk/imx/clk-lpcg-scu.c
> +++ b/drivers/clk/imx/clk-lpcg-scu.c
> @@ -6,6 +6,7 @@
> =20
>  #include <linux/bits.h>
>  #include <linux/clk-provider.h>
> +#include <linux/delay.h>
>  #include <linux/err.h>
>  #include <linux/io.h>
>  #include <linux/slab.h>
> @@ -41,6 +42,31 @@ struct clk_lpcg_scu {
> =20
>  #define to_clk_lpcg_scu(_hw) container_of(_hw, struct clk_lpcg_scu, hw)
> =20
> +/* e10858 -LPCG clock gating register synchronization errata */
> +static void lpcg_e10858_writel(ulong rate, void __iomem *reg, u32 val)

s/ulong/unsigned long/

> +{
> +       u32 reg1;
> +
> +       writel(val, reg);
> +
> +       if (rate >=3D 24000000 || rate =3D=3D 0) {

Can be '24 * HZ_PER_MHZ'

> +               /*
> +                * The time taken to access the LPCG registers from the A=
P core
> +                * through the interconnect is longer than the minimum de=
lay
> +                * of 4 clock cycles required by the errata.
> +                * Adding a readl will provide sufficient delay to prevent
> +                * back-to-back writes.
> +                */
> +               reg1 =3D readl(reg);
> +       } else {
> +               /*
> +                * For clocks running below 24MHz, wait a minimum of
> +                * 4 clock cycles.
> +                */
> +               ndelay(4 * (DIV_ROUND_UP(1000000000, rate)));

Can be '1000 * HZ_PER_MHZ'