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From: "Liang, Kan" <kan.liang@linux.intel.com>
To: Peter Zijlstra <peterz@infradead.org>
Cc: mingo@kernel.org, linux-kernel@vger.kernel.org, acme@kernel.org,
	namhyung@kernel.org, irogers@google.com, eranian@google.com,
	ak@linux.intel.com, yunying.sun@intel.com,
	tim.c.chen@linux.intel.com
Subject: Re: [PATCH V2 1/8] perf/x86/uncore: Save the unit control address of all units
Date: Mon, 17 Jun 2024 13:51:28 -0400	[thread overview]
Message-ID: <996eb980-ae88-4f02-bee3-cca511afcbd8@linux.intel.com> (raw)
In-Reply-To: <20240617155027.GX8774@noisy.programming.kicks-ass.net>



On 2024-06-17 11:50 a.m., Peter Zijlstra wrote:
> On Fri, Jun 14, 2024 at 06:46:24AM -0700, kan.liang@linux.intel.com wrote:
>> From: Kan Liang <kan.liang@linux.intel.com>
>>
>> The unit control address of some CXL units may be wrongly calculated
>> under some configuration on a EMR machine.
>>
>> The current implementation only saves the unit control address of the
>> units from the first die, and the first unit of the rest of dies. Perf
>> assumed that the units from the other dies have the same offset as the
>> first die. So the unit control address of the rest of the units can be
>> calculated. However, the assumption is wrong, especially for the CXL
>> units.
> 
> Oh gawd, that's terrible. Was this actually specified, or are we hacking
> around a firmware fail?

Not a workaround for a firmware fail. The the CXL discovery units depend
on the stacks and CXL devices present on each socket. So different
number of CXL devices on each socket is a valid combination.
SW cannot calculate the address of the devices on the other sockets via
the first socket. Full addresses have to be used.

Thanks,
Kan

  reply	other threads:[~2024-06-17 17:51 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-06-14 13:46 [PATCH V2 0/8] Support HBM and CXL PMON uncore counters kan.liang
2024-06-14 13:46 ` [PATCH V2 1/8] perf/x86/uncore: Save the unit control address of all units kan.liang
2024-06-17 15:50   ` Peter Zijlstra
2024-06-17 17:51     ` Liang, Kan [this message]
2024-06-24 15:09   ` [tip: perf/core] " tip-bot2 for Kan Liang
2024-06-14 13:46 ` [PATCH V2 2/8] perf/x86/uncore: Support per PMU cpumask kan.liang
2024-06-24 15:09   ` [tip: perf/core] " tip-bot2 for Kan Liang
2024-06-14 13:46 ` [PATCH V2 3/8] perf/x86/uncore: Retrieve the unit ID from the unit control RB tree kan.liang
2024-06-24 15:09   ` [tip: perf/core] " tip-bot2 for Kan Liang
2024-06-14 13:46 ` [PATCH V2 4/8] perf/x86/uncore: Apply the unit control RB tree to MMIO uncore units kan.liang
2024-06-24 15:09   ` [tip: perf/core] " tip-bot2 for Kan Liang
2024-06-14 13:46 ` [PATCH V2 5/8] perf/x86/uncore: Apply the unit control RB tree to MSR " kan.liang
2024-06-24 15:09   ` [tip: perf/core] " tip-bot2 for Kan Liang
2024-06-14 13:46 ` [PATCH V2 6/8] perf/x86/uncore: Apply the unit control RB tree to PCI " kan.liang
2024-06-24 15:09   ` [tip: perf/core] " tip-bot2 for Kan Liang
2024-06-14 13:46 ` [PATCH V2 7/8] perf/x86/uncore: Cleanup unused unit structure kan.liang
2024-06-24 15:09   ` [tip: perf/core] " tip-bot2 for Kan Liang
2024-06-14 13:46 ` [PATCH V2 8/8] perf/x86/intel/uncore: Support HBM and CXL PMON counters kan.liang
2024-06-24 15:09   ` [tip: perf/core] " tip-bot2 for Kan Liang

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