From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 93344C433F5 for ; Tue, 19 Apr 2022 12:46:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1352392AbiDSMsu (ORCPT ); Tue, 19 Apr 2022 08:48:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40280 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350314AbiDSMst (ORCPT ); Tue, 19 Apr 2022 08:48:49 -0400 Received: from ssl.serverraum.org (ssl.serverraum.org [176.9.125.105]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8FFAD35DC3 for ; Tue, 19 Apr 2022 05:46:04 -0700 (PDT) Received: from ssl.serverraum.org (web.serverraum.org [172.16.0.2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id 556242223A; Tue, 19 Apr 2022 14:46:02 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1650372362; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=zdmczezhx/tpLA3z8mH/wGkfcsWv93c1p3+6YiunEDo=; b=TJN8RIQZoIAzq2TksZMMhDozCaRhbLdSsvng6TjQ+ZMl6yXee+/HEXZEYG1qWAyCRX0EO+ +DP0ozooPtqaiyK13MoHI6+y8robdkYgAW4BIR4iFHZFK0/eJuzK/KwdMNWF0lmhSKaFr1 6jlGF22HPFONPL8767smkef5jH4kQng= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Date: Tue, 19 Apr 2022 14:46:02 +0200 From: Michael Walle To: Pratyush Yadav Cc: Tudor.Ambarus@microchip.com, miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, Nicolas.Ferre@microchip.com, Takahiro.Kuwano@infineon.com Subject: Re: [PATCH v3 6/9] mtd: spi-nor: core: Add helpers to read/write any register In-Reply-To: <20220419123245.zu4hypebz77ckygn@ti.com> References: <20220411091033.98754-1-tudor.ambarus@microchip.com> <20220411091033.98754-7-tudor.ambarus@microchip.com> <0e4ec58c21490dcd9cf82ab89bd8c34c@walle.cc> <20220419123245.zu4hypebz77ckygn@ti.com> User-Agent: Roundcube Webmail/1.4.13 Message-ID: <996f36b1303d191e472f56393aa6398e@walle.cc> X-Sender: michael@walle.cc Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Am 2022-04-19 14:32, schrieb Pratyush Yadav: > On 19/04/22 12:08PM, Tudor.Ambarus@microchip.com wrote: >> On 4/19/22 14:46, Michael Walle wrote: >> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe >> > >> > Am 2022-04-19 13:19, schrieb Michael Walle: >> >> Am 2022-04-11 11:10, schrieb Tudor Ambarus: >> >>> There are manufacturers that use registers indexed by address. Some of >> >>> them support "read/write any register" opcodes. Provide core methods >> >>> that >> >>> can be used by all manufacturers. SPI NOR controller ops are >> >>> intentionally >> >>> not supported as we intend to move all the SPI NOR controller drivers >> >>> under the SPI subsystem. >> >>> >> >>> Signed-off-by: Tudor Ambarus >> >>> Tested-by: Takahiro Kuwano >> >>> Reviewed-by: Pratyush Yadav >> >> >> >> I still don't like it because the function doesn't do >> >> anything what the function name might suggest. The read >> >> just executes an op, the write executes an op with a >> >> write enable before. All the behavior is determined by the >> >> 'op' argument. >> >> >> >> Anyway, >> >> Reviewed-by: Michael Walle >> >> >> >>> --- >> >>> v3: no changes >> >>> >> >>>  drivers/mtd/spi-nor/core.c | 41 >> >>> ++++++++++++++++++++++++++++++++++++++ >> >>>  drivers/mtd/spi-nor/core.h |  4 ++++ >> >>>  2 files changed, 45 insertions(+) >> >>> >> >>> diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c >> >>> index 6165dc7bfd17..42794328d3b6 100644 >> >>> --- a/drivers/mtd/spi-nor/core.c >> >>> +++ b/drivers/mtd/spi-nor/core.c >> >>> @@ -307,6 +307,47 @@ ssize_t spi_nor_write_data(struct spi_nor *nor, >> >>> loff_t to, size_t len, >> >>>      return nor->controller_ops->write(nor, to, len, buf); >> >>>  } >> >>> >> >>> +/** >> >>> + * spi_nor_read_reg() - read register to flash memory >> >>> + * @nor:        pointer to 'struct spi_nor'. >> >>> + * @op:             SPI memory operation. op->data.buf must be DMA-able. >> >>> + * @proto:  SPI protocol to use for the register operation. >> >>> + * >> >>> + * Return: zero on success, -errno otherwise >> >>> + */ >> >>> +int spi_nor_read_reg(struct spi_nor *nor, struct spi_mem_op *op, >> >>> +                 enum spi_nor_protocol proto) >> >>> +{ >> >>> +    if (!nor->spimem) >> >>> +            return -EOPNOTSUPP; >> >>> + >> >>> +    spi_nor_spimem_setup_op(nor, op, proto); >> >>> +    return spi_nor_spimem_exec_op(nor, op); >> >>> +} >> >>> + >> >>> +/** >> >>> + * spi_nor_write_reg() - write register to flash memory >> >>> + * @nor:        pointer to 'struct spi_nor' >> >>> + * @op:             SPI memory operation. op->data.buf must be DMA-able. >> >>> + * @proto:  SPI protocol to use for the register operation. >> >>> + * >> >>> + * Return: zero on success, -errno otherwise >> >>> + */ >> >>> +int spi_nor_write_reg(struct spi_nor *nor, struct spi_mem_op *op, >> >>> +                  enum spi_nor_protocol proto) >> >>> +{ >> >>> +    int ret; >> >>> + >> >>> +    if (!nor->spimem) >> >>> +            return -EOPNOTSUPP; >> >>> + >> >>> +    ret = spi_nor_write_enable(nor); >> >>> +    if (ret) >> >>> +            return ret; >> >>> +    spi_nor_spimem_setup_op(nor, op, proto); >> >>> +    return spi_nor_spimem_exec_op(nor, op); >> > >> > After seeing your next two patches. Shouldn't the >> > spi_nor_wait_until_ready() call be here too? >> > >> >> I thought of this too, but seems that for a reason that I don't >> remember, we don't call for spi_nor_wait_until_ready after we >> write the octal DTR bit. Pratyush, do you remember why? > > We are not sure the protocol changed correctly so we can't rely on > spi_nor_wait_until_ready(). We read the ID instead to be sure. So besides the fact that the write_reg only works with the 'correct' op parameter, it is also tailored to the special use case. For real write_reg(), the user would actually has to poll the status bit afterwards? :( -michael