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client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by SA2PEPF0000150B.mail.protection.outlook.com (10.167.242.43) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9891.9 via Frontend Transport; Tue, 5 May 2026 16:41:37 +0000 Received: from SATLEXMB04.amd.com (10.181.40.145) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.17; Tue, 5 May 2026 11:41:35 -0500 Received: from satlexmb07.amd.com (10.181.42.216) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 5 May 2026 11:41:35 -0500 Received: from [10.254.92.56] (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server id 15.2.2562.17 via Frontend Transport; Tue, 5 May 2026 11:41:33 -0500 Message-ID: <99c2f84f-6453-419a-b7bd-c4fb6cda85e0@amd.com> Date: Tue, 5 May 2026 12:41:33 -0400 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 2/2] drm/amd/display: add DMU timeout recovery support From: Leo Li To: Hamza Mahfooz , CC: Harry Wentland , Rodrigo Siqueira , Alex Deucher , =?UTF-8?Q?Christian_K=C3=B6nig?= , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Mario Limonciello , Alex Hung , Ray Wu , Wayne Lin , Aurabindo Pillai , =?UTF-8?Q?Timur_Krist=C3=B3f?= , "Mario Limonciello (AMD)" , Ivan Lipski , Chenyu Chen , Matthew Schwartz , Yussuf Khalil , Tom Chung , Colin Ian King , Charlene Liu , , References: <20260501203552.749080-1-someguy@effective-light.com> <20260501203552.749080-2-someguy@effective-light.com> <62c4c0e9-6368-4737-afc9-d4b1fa7a94e7@amd.com> Content-Language: en-US In-Reply-To: <62c4c0e9-6368-4737-afc9-d4b1fa7a94e7@amd.com> Content-Type: text/plain; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: KPaQR1T5KQYeT13ZUTYTvbH8IKyIWF5/j0WwArq9og6CgmuYkUlqqjgGSKZHW2HoqbzRwC2aUp3BIO3E3C96ha9vAV6zQRiz61njr3f6Ltxq0InX0EcuVH/7tiJdz4zvOUtAyCxY7TbP3t54/isfuHaoEqMioVnLWnVLsmaB/E9tmTjw46acjv5f86VA+AOTWNLuxJ4bb8zAXGuF3OPlMnSHhs1GPSBHv9yxHo7FZ6Tbvexrr7qHcxT2lBwqNWE1UJS+DyJ+fOopQvTEwTnYYsLRufPccYgwPjEtDYxDKoBB84HAw46/ul9qsUY1A9mYmxj78j+v9ahM45ARnGk1zGI2usFrzk/mNMrZp6xvB7HSeDdwX4kuucfumrlMnyeSqqOWECBIa71e1XPsf+mnqnNoXaVpz/0B4Gjntu17cQXQHo1xq5nJRdqNtNsvgsQx X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 May 2026 16:41:37.3044 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 299a5f73-91ff-4649-cedf-08deaac52d03 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF0000150B.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB8285 On 2026-05-05 12:36, Leo Li wrote: > > > On 2026-05-05 12:02, Leo Li wrote: >>> + /* >>> + * Compositors will refuse to make forward progress unless we send >>> + * the previous flip's completion event. >>> + */ >>> + if (WARN_ON(acrtc->event)) { >>> + drm_crtc_send_vblank_event(&acrtc->base, acrtc->event); >>> + drm_crtc_vblank_put(&acrtc->base); >>> + } >> I would expect this WARN_ON to occur only after the 10s flip_done timeout expires, allowing 'this' commit to progress with the previously armed acrtc->event and ->pflip_status from the previous commit ('this' commit would be gated by drm_atomic_helper_wait_for_dependencies). >> >> In which case, we probably want to apply the same above hunk for the cursor path here and also raise a warning: https://elixir.bootlin.com/linux/v6.19.3/source/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c#L10170 > > Hmm, scratch that, looks like I didn't finish my own thought: > > I think this would also mean the compositor sent 'this' commit without waiting for the previous vblank event. IOW it's not that compositors refuse to make forward progress, but wait_for_dependencies() in kernel will wait for a flip_done completion that will never come. And that can be a long time, since the drm_crtc_commit_wait()s stack. > > Indeed, it seems to be the case in the dmesg log attached to this issue: https://gitlab.freedesktop.org/drm/amd/-/work_items/4809 > > The back-to-back WARN_ONs are likely from the hunk above, and one level up at https://elixir.bootlin.com/linux/v7.0.1/source/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c#L10186. The compositor attempts another commit soon after, and hits the series of timeouts within wait_for_dependencies(), before we hit the next series of WARN_ONs from the same locations. > > So ultimately, I don't think sending the event here will do anything. Since by the time we hit that WARN_ON, we've already waited through wait_for_dependencies(). At which point, there aren't anymore waiters on it. > > I'm thinking an alternative would be to issue a 1-2s delayed worker whenever prepare_flip_isr() is called. The worker is canceled whenever the event is sent from the irq handlers. If it runs, then the expected pflip interrupt never fired, so we deliver the event in the worker. It's effectively a SW fallback for event delivery. > > Of course, it is only a fallback, ideally we figure out why interrupts were missed in the first place. > > - Leo (Apologies for the spam) But regarding this patch, I'm OK with dropping the above hunk but leaving the dm_helpers_dmu_timeout() implementation. With that change, this is Reviewed-by: Leo Li