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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CY4PEPF0000C97D.mail.protection.outlook.com (10.167.241.136) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6156.12 via Frontend Transport; Mon, 27 Feb 2023 08:17:20 +0000 Received: from [10.254.241.51] (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Mon, 27 Feb 2023 02:17:16 -0600 Message-ID: <9a4448cf-9064-c763-8887-791c4518af8e@amd.com> Date: Mon, 27 Feb 2023 09:16:58 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.8.0 Content-Language: en-US To: Swati Agarwal , , , CC: , , , References: <20230223141402.23979-1-swati.agarwal@amd.com> From: Michal Simek Subject: Re: [PATCH] mmc: sdhci-of-arasan: Add support to request the "gate" clock In-Reply-To: <20230223141402.23979-1-swati.agarwal@amd.com> Content-Type: text/plain; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Feb 2023 08:17:20.6660 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 52539c99-13a0-4909-bc10-08db189b0c42 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000C97D.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB6951 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2/23/23 15:14, Swati Agarwal wrote: > Add support to read the optional "gate" clock property and request the > clock which will be used to ungate the DLL clock. > > For Xilinx platforms which has DLL module, dll clock must be > ungated/enabled when SD controller operates at higher frequencies like 50 > MHz, 100 MHz and 200 MHz. This will be done by explicitly requesting gate > clock from the driver. > > Signed-off-by: Swati Agarwal > --- > drivers/mmc/host/sdhci-of-arasan.c | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/mmc/host/sdhci-of-arasan.c > index 4eebbf801b41..1fd7528c14fc 100644 > --- a/drivers/mmc/host/sdhci-of-arasan.c > +++ b/drivers/mmc/host/sdhci-of-arasan.c > @@ -1870,6 +1870,7 @@ static int sdhci_arasan_probe(struct platform_device *pdev) > int ret; > struct device_node *node; > struct clk *clk_xin; > + struct clk *clk_dll; > struct sdhci_host *host; > struct sdhci_pltfm_host *pltfm_host; > struct device *dev = &pdev->dev; > @@ -1943,6 +1944,12 @@ static int sdhci_arasan_probe(struct platform_device *pdev) > goto clk_dis_ahb; > } > > + clk_dll = devm_clk_get_optional_enabled(dev, "gate"); > + if (IS_ERR(clk_dll)) { > + ret = dev_err_probe(dev, PTR_ERR(clk_dll), "failed to get dll clk\n"); > + goto clk_disable_all; > + } > + > if (of_property_read_bool(np, "xlnx,fails-without-test-cd")) > sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_FORCE_CDTEST; > Based on available information, that it is not clear what gate clock really is and what it is used for, I think the patch is correct. Acked-by: Michal Simek Thanks, Michal