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From: "Chen, Zide" <zide.chen@intel.com>
To: Ingo Molnar <mingo@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>,
	Ingo Molnar <mingo@redhat.com>,
	Arnaldo Carvalho de Melo <acme@kernel.org>,
	Namhyung Kim <namhyung@kernel.org>,
	Ian Rogers <irogers@google.com>,
	Adrian Hunter <adrian.hunter@intel.com>,
	Alexander Shishkin <alexander.shishkin@linux.intel.com>,
	Andi Kleen <ak@linux.intel.com>,
	Eranian Stephane <eranian@google.com>,
	linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org,
	Dapeng Mi <dapeng1.mi@linux.intel.com>,
	Xudong Hao <xudong.hao@intel.com>,
	Falcon Thomas <thomas.falcon@intel.com>,
	Artem Bityutskiy <artem.bityutskiy@intel.com>,
	Kan Liang <kan.liang@linux.intel.com>,
	Zhenyu Wang <zhenyuw.linux@gmail.com>
Subject: Re: [PATCH RESEND 1/3] perf/x86/intel/cstate: Add Clearwater Forest support
Date: Thu, 30 Oct 2025 10:38:56 -0700	[thread overview]
Message-ID: <9c21d7e0-fcfd-43c2-ba5d-5881400a46ca@intel.com> (raw)
In-Reply-To: <aQMrONyVjGsCFXe2@gmail.com>



On 10/30/2025 2:09 AM, Ingo Molnar wrote:
> 
> * Zide Chen <zide.chen@intel.com> wrote:
> 
>> Clearwater Forest is based on the Darkmont Atom microarchitecture.
>> From the perspective of C-state residency profiling, it supports the
>> same residency counters as Sierra Forest: CC1/CC6, PC2/PC6, and MC6.
>>
>> Please note that the C1E residency counter can only be read via PMT,
>> not MSR. Therefore, tools relying on the perf_event framework cannot
>> access the C1E residency.
>>
>> Cc: Artem Bityutskiy <artem.bityutskiy@intel.com>
>> Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
>> Signed-off-by: Zhenyu Wang <zhenyuw.linux@gmail.com>
>> Signed-off-by: Zide Chen <zide.chen@intel.com>
> 
> So, this is not a valid SOB chain: primary author should be the first 
> SOB, or if it was co-developed, it should have the proper 
> Co-developed-by tags.
> 
> Here I can see two possibilities:
> 
> (1) if Zhenyu Wang was the primary author, and Zide Chen reviewed, 
>     tested and submitted it upstream, then:
> 
> 
>   | From: Zide Chen <zide.chen@intel.com>
>   | Subject: [PATCH 1/3] perf/x86/intel/cstate: Add Clearwater Forest support
> 
>     From: Zhenyu Wang <zhenyuw.linux@gmail.com>
>     ...
> 
>     Signed-off-by: Zhenyu Wang <zhenyuw.linux@gmail.com>
>     Signed-off-by: Zide Chen <zide.chen@intel.com>
> 
> (I.e. add the extra From line as the first line of the changelog.)

Yes, that is the case.
Thank you very much for pointing this out! I will pay extra attention to
the SoB chain going forward.


> (2) if it was co-developed, with Zhenyu Wang and Zide Chen having each 
>     written unique lines of code of their own that finally resulted in 
>     this submission, then:
> 
>   | From: Zide Chen <zide.chen@intel.com>
>   | Subject: [PATCH 1/3] perf/x86/intel/cstate: Add Clearwater Forest support
> 
>     ...
> 
>     Co-developed-by: Zide Chen <zide.chen@intel.com>
>     Signed-off-by: Zide Chen <zide.chen@intel.com>
>     Co-developed-by: Zhenyu Wang <zhenyuw.linux@gmail.com>
>     Signed-off-by: Zhenyu Wang <zhenyuw.linux@gmail.com>
> 
> Which one was it? :-)
> 
> Thanks,
> 
> 	Ingo


  reply	other threads:[~2025-10-30 17:38 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-10-23 22:37 [PATCH RESEND 0/3] cstate support for CWF, LNL and PTL Zide Chen
2025-10-23 22:37 ` [PATCH RESEND 1/3] perf/x86/intel/cstate: Add Clearwater Forest support Zide Chen
2025-10-29  9:36   ` [tip: perf/core] " tip-bot2 for Zide Chen
2025-10-30  9:09   ` [PATCH RESEND 1/3] " Ingo Molnar
2025-10-30 17:38     ` Chen, Zide [this message]
2025-10-23 22:37 ` [PATCH RESEND 2/3] perf/x86/intel/cstate: Remove PC3 support from LunarLake Zide Chen
2025-10-29  9:36   ` [tip: perf/core] " tip-bot2 for Zhang Rui
2025-10-23 22:37 ` [PATCH RESEND 3/3] perf/x86/intel/cstate: Add Pantherlake support Zide Chen
2025-10-29  9:36   ` [tip: perf/core] " tip-bot2 for Zhang Rui
2025-10-24  7:43 ` [PATCH RESEND 0/3] cstate support for CWF, LNL and PTL Mi, Dapeng

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