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Thu, 1 Nov 2018 05:02:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1541048551; bh=Do00PobtbZla7MZ3DLlGPN3rzOic9p3z4301VRbKRgc=; h=Subject:To:Cc:References:From:Date:In-Reply-To:From; b=nFcQ3sPDQ1VUa3P1Yk7org8SxXJX8JivSiBQQssOHLMq+zN5A2v22oKvSn7yoz12S vlv97JGwreH3QLPLDmPvY+dI4az7e8b0o4lWXRL75h0uYVqmILNyubVsScAMILdvDX sdrhFgp+V9LfDak4m7yEY6QXJIFctq2v2SbHkQcM= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 2A85C6014B Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=tdas@codeaurora.org Subject: Re: [PATCH v1 2/2] clk: qcom : dispcc: Add support for display port clocks To: Stephen Boyd , Michael Turquette , chandanu@codeaurora.org Cc: Andy Gross , David Brown , Rajendra Nayak , linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, chandanu@codeaurora.org, linux-arm-msm-owner@vger.kernel.org References: <1539093467-12123-1-git-send-email-tdas@codeaurora.org> <1539093467-12123-3-git-send-email-tdas@codeaurora.org> <153911726378.119890.5522594539667887860@swboyd.mtv.corp.google.com> <3c4cccca-2c5c-927f-f471-2bbbd71b4155@codeaurora.org> <9c359e26-3708-14b6-f22a-fb529446d325@codeaurora.org> <154083859263.98144.15690571729193618604@swboyd.mtv.corp.google.com> <154091723693.98144.6979314028521443413@swboyd.mtv.corp.google.com> From: Taniya Das Message-ID: <9c82010f-f3fd-2867-352e-3584ab4ba8f0@codeaurora.org> Date: Thu, 1 Nov 2018 10:32:22 +0530 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:52.0) Gecko/20100101 Thunderbird/52.9.1 MIME-Version: 1.0 In-Reply-To: <154091723693.98144.6979314028521443413@swboyd.mtv.corp.google.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org + Chandan from Display Port team, On 10/30/2018 10:03 PM, Stephen Boyd wrote: > Quoting Taniya Das (2018-10-29 23:01:44) >> On 10/30/2018 12:13 AM, Stephen Boyd wrote: >>> Quoting Taniya Das (2018-10-28 03:34:55) >>>> On 2018-10-19 16:04, Taniya Das wrote: >>>>> On 10/10/2018 2:04 AM, Stephen Boyd wrote: >>>>>> Quoting Taniya Das (2018-10-09 06:57:47) >>>>>>> diff --git a/drivers/clk/qcom/dispcc-sdm845.c >>>>>>> b/drivers/clk/qcom/dispcc-sdm845.c >>>>>>> index 0cc4909..6d3136a 100644 >>>>>>> --- a/drivers/clk/qcom/dispcc-sdm845.c >>>>>>> +++ b/drivers/clk/qcom/dispcc-sdm845.c >>>>>>> + }, >>>>>>> +}; >>>>>>> + >>>>>>> +static const struct freq_tbl ftbl_disp_cc_mdss_dp_link_clk_src[] = { >>>>>>> + F(162000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), >>>>>>> + F(270000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), >>>>>>> + F(540000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), >>>>>>> + F(810000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), >>>>>> >>>>>> Are these in kHz? They really look like it and that's bad. Why do we >>>>>> need them at all? Just to make sure the display driver picks these >>>>>> exact >>>>>> frequencies? It seems like we could just pass whatever number comes in >>>>>> up to the parent and see what it can do. >>>>>> >>>>> >>>>> Let me check back the reason we had to make this change. >>>> >>>> We will need this flag since we reset/power-down the PLL every time we >>>> disconnect/connect the DP cable or during suspend/resume. Only with this >>>> flag, the calls to the PLL driver are properly called. >>> >>> What does this mean? I wanted to know about the weird frequencies listed >>> above, and why it can't be done without a frequency table and direct >>> rates passed up to the parent. >>> >> >> OOps, my bad :(. >> >> We added these changes to handle higher clock rates. These rates when >> greater than 4.3Ghz cannot be represented in 32bit variables. For DP, we >> already have 5.4G and 8.1GHz freq for VCO clock. We will need these Khz >> freq list in clock driver. >> Let me check if they can do something like the byte/pixel clocks of >> display. > > Well then we really should just throw away the freq table here and have > rcg ops that pass the frequency up to the display PLL. Also, those > numbers look like gigabits per second (Gbit/s) for the DP spec which > isn't exactly the same as a clk frequency. What frequency does the PLL > run at for these various DP link speeds? > Could you please help with the above query from Stephen? -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation. --