Re: [PATCH v2 1/8] dt-bindings: PCI: Add binding for qps615

[Krzysztof Kozlowski <krzk@kernel.org>]

On 22/08/2024 16:16, Manivannan Sadhasivam wrote:
> On Mon, Aug 05, 2024 at 04:43:47PM +0200, Krzysztof Kozlowski wrote:
>> On 05/08/2024 07:57, Krishna Chaitanya Chundru wrote:
>>>>
>>> Hi Krzysztof,
>>>
>>> QPS615 has a 3 downstream ports and 1 upstream port as described below
>>> diagram.
>>> For this entire switch there are some supplies which we described in the
>>> dt-binding (vdd18-supply, vdd09-supply etc) and one GPIO which controls
>>> reset of the switch (reset-gpio). The switch hardware can configure the
>>> individual ports DSP0, DSP1, DSP2, upstream port and also one integrated
>>> ethernet endpoint which is connected to DSP2(I didn't mentioned in the
>>> diagram) through I2C.
>>>
>>> The properties other than supplies,i2c client, reset gpio which
>>> are added will be applicable for all the ports.
>>> _______________________________________________________________
>>> |   |i2c|                   QPS615       |Supplies||Resx gpio |
>>> |   |___|              _________________ |________||__________|
>>> |      ________________| Upstream port |_____________         |
>>> |      |               |_______________|            |         |
>>> |      |                       |                    |         |
>>> |      |                       |                    |         |
>>> |  ____|_____              ____|_____            ___|____     |
>>> |  |DSP 0   |              | DSP 1  |            | DSP 2|     |
>>> |  |________|              |________|            |______|     |
>>> |_____________________________________________________________|
>>>
>>
>> I don't get why then properties should apply to main device node.
>>
> 
> The problem here is, we cannot differentiate between main device node and the
> upstream node. Typically the differentiation is not needed because no one cared
> about configuring the upstream port. But this PCIe switch is special (as like
> most of the Qcom peripherals).
> 
> I agree that if we don't differentiate then it also implies that all main node
> properties are applicable to upstream port and vice versa. But AFAIK, upstream
> port is often considered as the _device_ itself as it shares the same bus
> number.

Well, above diagram shows supplies being part of the entire device, not
each port. That's confusing. Based on diagram, downstream ports do not
have any supplies... and what exactly do they supply? Let's look at
vdd18 and vdd09 which sound main supplies of the entire device. In
context of port: what exactly do they power? Which part of the port?

Best regards,
Krzysztof