From: Reinette Chatre <reinette.chatre@intel.com>
To: <babu.moger@amd.com>, <corbet@lwn.net>, <tglx@linutronix.de>,
<mingo@redhat.com>, <bp@alien8.de>, <dave.hansen@linux.intel.com>,
<x86@kernel.org>
Cc: <fenghua.yu@intel.com>, <hpa@zytor.com>, <paulmck@kernel.org>,
<thuth@redhat.com>, <xiongwei.song@windriver.com>,
<ardb@kernel.org>, <pawan.kumar.gupta@linux.intel.com>,
<daniel.sneddon@linux.intel.com>, <sandipan.das@amd.com>,
<kai.huang@intel.com>, <peterz@infradead.org>,
<kan.liang@linux.intel.com>, <pbonzini@redhat.com>,
<xin3.li@intel.com>, <ebiggers@google.com>,
<alexandre.chartre@oracle.com>, <perry.yuan@amd.com>,
<tan.shaopeng@fujitsu.com>, <james.morse@arm.com>,
<tony.luck@intel.com>, <maciej.wieczor-retman@intel.com>,
<linux-doc@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<peternewman@google.com>, <eranian@google.com>
Subject: Re: [PATCH 5/7] x86/resctrl: Add interface to enable/disable SDCIAE
Date: Wed, 16 Oct 2024 08:53:50 -0700 [thread overview]
Message-ID: <9d52bac8-5e4c-4bd2-b01d-c78d4b7274d6@intel.com> (raw)
In-Reply-To: <a6a1dde1-5b4c-4c3e-a9e7-b2f2b327894e@amd.com>
Hi Babu,
On 10/15/24 12:25 PM, Moger, Babu wrote:
> Hi Reinette,
>
> Noticed I didn't respond to this comment.
>
> On 9/19/24 10:35, Reinette Chatre wrote:
>> Hi Babu,
>>
>> On 9/18/24 1:10 PM, Moger, Babu wrote:
>>> On 9/13/24 15:51, Reinette Chatre wrote:
>>>> On 8/16/24 9:16 AM, Babu Moger wrote:
>>
>> ...
>>
>>>>> + if (enable) {
>>>>> + ret = closid_alloc_sdciae(r);
>>>>> + if (ret < 0) {
>>>>> + rdt_last_cmd_puts("SDCIAE CLOSID is not available\n");
>>>>> + goto out_sdciae;
>>>>> + }
>>>>> + } else {
>>>>> + sdciae_closid = get_sdciae_closid(r);
>>>>> + closid_free(sdciae_closid);
>>>>> + }
>>>>
>>>>
>>>>> +
>>>>> + ret = resctrl_arch_set_sdciae_enabled(RDT_RESOURCE_L3, enable);
>>>>
>>>> I assume that once SDCIAE is enabled the I/O traffic will start flowing to
>>>> whatever
>>>> was the last CBM of the max CLOSID? Is this intended or should there be
>>>> some default
>>>> CBM that this feature should start with?
>>>
>>> It will start with whatever the last CBM for max CLOSID.
>>
>> This seems arbitrary based on whatever allocation the previous resource group
>> using the CLOSID has. When a new resource group is created resctrl ensures
>> that it is created with all usable allocations, see rdtgroup_init_cat().
>
> Checked again with with the team here. When SDCIAE is enabled, it uses the
> value in L3QosAllocMask15 (value in L3_MASK_15 MSR). Enabling SDCIAE does
> not change the value of L3QosAllocMask15.
I see the issue as similar to how resource group allocations are managed.
Just like resctrl ensures that when a new resource group is created, it is done
with maximum allocations that the resource group may use ... not the allocations
left over from the previous resource group that used those MSRs.
I understand that the hardware uses L3QosAllocMask15 and does not change
L3QosAllocMask15 when SDCIAE is enabled, but resctrl is in a position to initialize
those registers at the time when SDCIAE is initialized to create a sane default
allocation, not an allocation of whatever happened to be in MSR at that time.
>> Letting cache injection start with whatever allocation remnant programmed
>> in a register does not seem ideal. What if, for example, after that resource
>> group was removed, a new exclusive resource group was created that overlaps
>> with that allocation?
>
> In that case. it will share the bit mask with the exclusive group. We may
> need to add a text about it.
No. This can be avoided entirely when resctrl initializes the MSR to a sane
default, no?
Reinette
next prev parent reply other threads:[~2024-10-16 15:54 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-16 16:16 [PATCH 0/7] x86/resctrl : Support L3 Smart Data Cache Injection Allocation Enforcement (SDCIAE) Babu Moger
2024-08-16 16:16 ` [PATCH 1/7] x86/cpufeatures: Add support for L3 Smart Data Cache Injection Allocation Enforcement Babu Moger
2024-08-17 14:50 ` Borislav Petkov
2024-08-19 20:17 ` Moger, Babu
2024-09-13 20:44 ` Reinette Chatre
2024-09-18 0:50 ` Moger, Babu
2024-08-16 16:16 ` [PATCH 2/7] x86/resctrl: Add SDCIAE feature in the command line options Babu Moger
2024-09-13 20:45 ` Reinette Chatre
2024-09-18 14:38 ` Moger, Babu
2024-08-16 16:16 ` [PATCH 3/7] x86/resctrl: Introduce sdciae_capable in rdt_resource Babu Moger
2024-09-13 20:45 ` Reinette Chatre
2024-09-18 15:27 ` Moger, Babu
2024-09-18 18:22 ` Moger, Babu
2024-09-19 15:33 ` Reinette Chatre
2024-09-20 21:05 ` Moger, Babu
2024-10-15 20:40 ` Moger, Babu
2024-10-16 15:54 ` Reinette Chatre
2024-10-16 16:46 ` Moger, Babu
2024-10-16 18:31 ` Reinette Chatre
2024-08-16 16:16 ` [PATCH 4/7] x86/resctrl: Implement SDCIAE enable/disable Babu Moger
2024-09-13 20:46 ` Reinette Chatre
2024-09-18 16:26 ` Moger, Babu
2024-09-19 15:34 ` Reinette Chatre
2024-09-20 21:33 ` Moger, Babu
2024-08-16 16:16 ` [PATCH 5/7] x86/resctrl: Add interface to enable/disable SDCIAE Babu Moger
2024-09-13 20:51 ` Reinette Chatre
2024-09-18 20:10 ` Moger, Babu
2024-09-19 15:35 ` Reinette Chatre
2024-10-15 19:25 ` Moger, Babu
2024-10-16 15:53 ` Reinette Chatre [this message]
2024-10-16 16:52 ` Moger, Babu
2024-08-16 16:16 ` [PATCH 6/7] x86/resctrl: Introduce interface to display SDCIAE Capacity Bit Masks Babu Moger
2024-09-13 20:52 ` Reinette Chatre
2024-09-18 20:19 ` Moger, Babu
2024-08-16 16:16 ` [PATCH 7/7] x86/resctrl: Introduce interface to modify " Babu Moger
2024-09-13 20:44 ` [PATCH 0/7] x86/resctrl : Support L3 Smart Data Cache Injection Allocation Enforcement (SDCIAE) Reinette Chatre
2024-09-17 20:51 ` Moger, Babu
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=9d52bac8-5e4c-4bd2-b01d-c78d4b7274d6@intel.com \
--to=reinette.chatre@intel.com \
--cc=alexandre.chartre@oracle.com \
--cc=ardb@kernel.org \
--cc=babu.moger@amd.com \
--cc=bp@alien8.de \
--cc=corbet@lwn.net \
--cc=daniel.sneddon@linux.intel.com \
--cc=dave.hansen@linux.intel.com \
--cc=ebiggers@google.com \
--cc=eranian@google.com \
--cc=fenghua.yu@intel.com \
--cc=hpa@zytor.com \
--cc=james.morse@arm.com \
--cc=kai.huang@intel.com \
--cc=kan.liang@linux.intel.com \
--cc=linux-doc@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=maciej.wieczor-retman@intel.com \
--cc=mingo@redhat.com \
--cc=paulmck@kernel.org \
--cc=pawan.kumar.gupta@linux.intel.com \
--cc=pbonzini@redhat.com \
--cc=perry.yuan@amd.com \
--cc=peternewman@google.com \
--cc=peterz@infradead.org \
--cc=sandipan.das@amd.com \
--cc=tan.shaopeng@fujitsu.com \
--cc=tglx@linutronix.de \
--cc=thuth@redhat.com \
--cc=tony.luck@intel.com \
--cc=x86@kernel.org \
--cc=xin3.li@intel.com \
--cc=xiongwei.song@windriver.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox