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Fri, 21 Jun 2024 07:04:50 -0400 (EDT) X-Mailer: MessagingEngine.com Webmail Interface User-Agent: Cyrus-JMAP/3.11.0-alpha0-522-ga39cca1d5-fm-20240610.002-ga39cca1d Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <9d64bd8d-e146-46e7-8526-e85192ee14ed@app.fastmail.com> In-Reply-To: References: <20240511104341.151550-1-aleksandar.rikalo@syrmia.com> Date: Fri, 21 Jun 2024 12:04:30 +0100 From: "Jiaxun Yang" To: "Thomas Bogendoerfer" Cc: "Aleksandar Rikalo" , "Aleksandar Rikalo" , "Chao-ying Fu" , "Daniel Lezcano" , "Geert Uytterhoeven" , "Greg Ungerer" , "Hauke Mehrtens" , "Ilya Lipnitskiy" , linux-kernel@vger.kernel.org, "linux-mips@vger.kernel.org" , "Marc Zyngier" , "paulburton@kernel.org" , "Peter Zijlstra" , "Serge Semin" , "Thomas Gleixner" , "Tiezhu Yang" Subject: Re: [PATCH v4 00/14] MIPS: Support I6500 multi-cluster configuration Content-Type: text/plain;charset=utf-8 Content-Transfer-Encoding: quoted-printable =E5=9C=A82024=E5=B9=B46=E6=9C=8821=E6=97=A5=E5=85=AD=E6=9C=88 =E4=B8=8A=E5= =8D=889:21=EF=BC=8CThomas Bogendoerfer=E5=86=99=E9=81=93=EF=BC=9A > On Fri, Jun 21, 2024 at 12:05:32AM +0100, Jiaxun Yang wrote: >>=20 >>=20 >> =E5=9C=A82024=E5=B9=B46=E6=9C=8820=E6=97=A5=E5=85=AD=E6=9C=88 =E4=B8=8B= =E5=8D=886:56=EF=BC=8CThomas Bogendoerfer=E5=86=99=E9=81=93=EF=BC=9A >> > On Sat, May 11, 2024 at 12:43:27PM +0200, Aleksandar Rikalo wrote: >> >> Taken from Paul Burton MIPS repo with minor changes from Chao-ying= Fu. >> >> Tested with 64r6el_defconfig on Boston board in 2 cluster/2 VPU and >> >> 1 cluster/4 VPU configurations. >> > >> > which existing CPUs can use this ? >>=20 >> Besides Boston are some multi cluster I6500 systems in wild, includin= g Fungible F1, >> which comes with 52 cores in data panel. >>=20 >> Those vendors show no interest on mainline kernel support though. > > ok, so looking at the series it touches areas with different maintaine= rs, > I'm fine taking the MIPS parts, can I simply cherry-pick them out > of the series ? For irqchip part I think it must be taken together with MIPS arch part. It's a part of MIPS CORE DRIVERS maintainers entry as well. For FDC I think functionally it's not a prerequisite. Thanks > > Thomas. > > --=20 > Crap can work. Given enough thrust pigs will fly, but it's not necessa= rily a > good idea. [ RFC1925, 2= .3 ] --=20 - Jiaxun