Re: User mode drivers: part 1, interrupt handling (patch for 2.6.11)

Lee Revell
2005-03-15T04:32:34Z

On Sat, 2005-03-12 at 21:03 -0500, Jon Smirl wrote:
> On Fri, 11 Mar 2005 19:14:13 +0000, Alan Cox <alan@lxorguk.ukuu.org.uk> wrote:
> > I posted a proposal for this sometime ago because X has some uses for
> > it. The idea being you'd pass a struct that describes
> >
> > 1. What tells you an IRQ occurred on this device
> > 2. How to clear it
> > 3. How to enable/disable it.
> >
> > Something like
> >
> > struct {
> > u8 type; /* 8, 16, 32 I/O or MMIO */
> > u8 bar; /* PCI bar to use */
> > u32 offset; /* Into bar */
> > u32 mask; /* Bits to touch/compare */
> > u32 value; /* Value to check against/set */
> > }
> >
>
> It might useful to add this to the main kernel API, and then over time
> modify all of the drivers to use it. If a driver does this it would be
> safe to transparently move it to user space like in UML or xen. I've
> been told that PCI Express and MSI does not have this problem.
>

This seems sufficient for the simplest devices, that just have an
IRQ_PENDING and an IRQ_ACK register. But what about a device like the
emu10k1 where you have a half loop and loop interrupt for each of 64
channels, plus about 10 other interrupt sources? The IPR just tells you
there's a channel loop interrupt pending, in order to properly ACK it
you need to set a bit in one of 4 registers depending on whether it's a
loop or half loop interrupt, and whether the channel is 0-31 or 32-64.

Lee