From: "H. Peter Anvin" <hpa@zytor.com>
To: linux-kernel@vger.kernel.org
Subject: Re: Setting up MTRRs for 4096MB RAM
Date: 9 Aug 2001 10:53:00 -0700 [thread overview]
Message-ID: <9kuils$q67$1@cesium.transmeta.com> (raw)
In-Reply-To: <Pine.LNX.4.21.0108091306550.18150-100000@willow.commerce.uk.net>
Followup to: <Pine.LNX.4.21.0108091306550.18150-100000@willow.commerce.uk.net>
By author: Corin Hartland-Swann <cdhs@commerce.uk.net>
In newsgroup: linux.dev.kernel
>
> I am trying to set up a machine using the Tyan Tiger LE motherboard, and
> ServerWorks III LE chipset to use 4096MB RAM. I'm using kernel 2.4.7 with
> CONFIG_HIGHMEM4G.
>
> I know that I have to set the MTRR's up to extend the cacheable memory
> area, but can't work out how to set it up.
>
> I tried the following:
>
> # echo "disable=1" >| /proc/mtrr
> # echo "disable=0" >| /proc/mtrr
> # echo "base=0x0 size=0xFFFFFFFF type=write-back" >| /proc/mtrr
> mtrr: size and base must be multiples of 4 kiB
> mtrr: size: 0xffffffff base: 0x0
>
> Which doesn't make any sense. So I tried for 3G RAM:
>
> # echo "base=0x0 size=0xC0000000 type=write-back" >| /proc/mtrr
> mtrr: base(0x0000) is not aligned on a size(0xc0000000) boundary
>
> And then for 2G RAM:
>
> # echo "base=0x0 size=0x80000000 type=write-back" >| /proc/mtrr
>
> Which works perfectly. What gives?
>
Intel MTRRs have to be a multiple of 2, so you'd need 2 MTRRs if you
wanted to cover 3 GB. 0x80000000 is a multiple of 2; 0xC0000000
isn't, and 0xFFFFFFFF definitely isn't, although 0x100000000 is.
I'm surprised you didn't see that very pattern in your own responses:
you are entering the full size in the working case, but then subtract
1 in the 4 GB case.
-hpa
--
<hpa@transmeta.com> at work, <hpa@zytor.com> in private!
"Unix gives you enough rope to shoot yourself in the foot."
http://www.zytor.com/~hpa/puzzle.txt <amsp@zytor.com>
next prev parent reply other threads:[~2001-08-09 17:53 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2001-08-09 12:18 Setting up MTRRs for 4096MB RAM Corin Hartland-Swann
2001-08-09 17:53 ` H. Peter Anvin [this message]
2001-08-09 18:06 ` Tim Walberg
2001-08-09 18:50 ` H. Peter Anvin
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