Re: Intel I860

["H. Peter Anvin" <hpa@zytor.com>]

Followup to:  <200112091201.fB9C1wD158088@saturn.cs.uml.edu>
By author:    "Albert D. Cahalan" <acahalan@cs.uml.edu>
In newsgroup: linux.dev.kernel
> 
> It's a RISC chip with the Pentium MMU. To get any speed out of it,
> you have to enable some strange features. First of all, you need
> the double-instruction mode. In every 64-bit chunk of memory you
> place 1 floating-point instruction and 1 integer instruction.
> Second of all, you need to enable pipelined FPU operation. This is
> an exposed pipeline, so watch out! Look what happens:
> 
> a = x + x
> b = a + a     <-- uses old value of "a", not x+x
> nop
> nop
> nop
> c = a + a
> 
> Yep, c!=a after this!  Actually, "c" won't be set until a few
> instructions later because it too is still in the pipeline.
> You need a few dummy operations to push it out.
> 

Nononon... it's much worse than that.

The i860 used a non-self-terminating pipeline, which meant that for
each instruction you had "what to stuff into the pipeline at this
stage" and "what to do with what comes out of the pipeline here",
which means that to compute d = a + b - c you'd have to do something
like:

X = a + b
nop
nop
nop
t = XXX
X = t - c
nop
nop
nop
d = XXX

... where X means don't care.  To compute, say, h = e + f - g in
parallel with this, it would look something like:

X = a + b
X = e + f
nop
nop
t = XXX
u = t - c
X = u - g
nop
nop
d = XXX
h = XXX

Note the instruction u = t - c, even though the left side and right
side don't even belong to the same thread of execution...

     -hpa
-- 
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