[PATCH] PCI updates - 32-bit IO support

[PATCH] PCI updates - 32-bit IO support

[Russell King]

I have here a system which requires 32-bit IO addressing on its PCI
busses.  Currently, Linux zeros the upper IO base/limit registers on
all PCI bridges, which prevents addresses being forwarded on this
system.

The following patch the upper IO base/limit registers to be set
appropriately by the PCI layer.

This patch is being sent for review, and is targetted solely at 2.5.

diff -ur orig/drivers/pci/setup-bus.c linux/drivers/pci/setup-bus.c
--- orig/drivers/pci/setup-bus.c	Sun Oct 14 20:53:14 2001
+++ linux/drivers/pci/setup-bus.c	Tue Dec 18 23:20:13 2001
@@ -148,7 +181,10 @@
 	pci_write_config_dword(bridge, PCI_IO_BASE, l);
 
 	/* Clear upper 16 bits of I/O base/limit. */
-	pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0);
+	pci_write_config_word(bridge, PCI_IO_BASE_UPPER16,
+			ranges.io_start >> 16);
+	pci_write_config_word(bridge, PCI_IO_LIMIT_UPPER16,
+			ranges.io_end >> 16);
 
 	/* Clear out the upper 32 bits of PREF base/limit. */
 	pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, 0);


--
Russell King (rmk@arm.linux.org.uk)                The developer of ARM Linux
             http://www.arm.linux.org.uk/personal/aboutme.html

Re: [PATCH] PCI updates - 32-bit IO support

[H. Peter Anvin]

Followup to:  <20011218235024.N13126@flint.arm.linux.org.uk>
By author:    Russell King <rmk@flint.arm.linux.org.uk>
In newsgroup: linux.dev.kernel
>
> I have here a system which requires 32-bit IO addressing on its PCI
> busses.  Currently, Linux zeros the upper IO base/limit registers on
> all PCI bridges, which prevents addresses being forwarded on this
> system.
> 
> The following patch the upper IO base/limit registers to be set
> appropriately by the PCI layer.
> 
> This patch is being sent for review, and is targetted solely at 2.5.
> 
> diff -ur orig/drivers/pci/setup-bus.c linux/drivers/pci/setup-bus.c
> --- orig/drivers/pci/setup-bus.c	Sun Oct 14 20:53:14 2001
> +++ linux/drivers/pci/setup-bus.c	Tue Dec 18 23:20:13 2001
> @@ -148,7 +181,10 @@
>  	pci_write_config_dword(bridge, PCI_IO_BASE, l);
>  
>  	/* Clear upper 16 bits of I/O base/limit. */
> -	pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0);
> +	pci_write_config_word(bridge, PCI_IO_BASE_UPPER16,
> +			ranges.io_start >> 16);
> +	pci_write_config_word(bridge, PCI_IO_LIMIT_UPPER16,
> +			ranges.io_end >> 16);
>  

You probably need to verify that 32-bit support is available (both on
the bridge and the peripherals), but if they are, there's no reason
not to use it on non-x86 architectures...

	-hpa
-- 
<hpa@transmeta.com> at work, <hpa@zytor.com> in private!
"Unix gives you enough rope to shoot yourself in the foot."
http://www.zytor.com/~hpa/puzzle.txt	<amsp@zytor.com>

Re: [PATCH] PCI updates - 32-bit IO support

[David S. Miller]

   From: "H. Peter Anvin" <hpa@zytor.com>
   Date: 19 Dec 2001 19:37:46 -0800
   
   You probably need to verify that 32-bit support is available (both on
   the bridge and the peripherals), but if they are, there's no reason
   not to use it on non-x86 architectures...

Don't the PCI specs actually talk about 24-bits in fact?

Russell does you box really have the full 32-bits or is it
really just 24-bits?

Re: [PATCH] PCI updates - 32-bit IO support

[H. Peter Anvin]

David S. Miller wrote:

>    From: "H. Peter Anvin" <hpa@zytor.com>
>    Date: 19 Dec 2001 19:37:46 -0800
>    
>    You probably need to verify that 32-bit support is available (both on
>    the bridge and the peripherals), but if they are, there's no reason
>    not to use it on non-x86 architectures...
> 
> Don't the PCI specs actually talk about 24-bits in fact?
> 


No.  IOIO is 32 bits on PCI; however, it is legal to hardwire the top 16 
bits to zero.  It's something like 26 bits on HyperTransport.

	-hpa

Re: [PATCH] PCI updates - 32-bit IO support

[Russell King]

On Wed, Dec 19, 2001 at 09:30:19PM -0800, David S. Miller wrote:
> Don't the PCI specs actually talk about 24-bits in fact?
> 
> Russell does you box really have the full 32-bits or is it
> really just 24-bits?

Shrug - the chip documentation isn't good enough to indicate either.

What I do know is:

- setting the bridge and eepro100 up with 16-bit IO addresses causes PCI
  master aborts.
- setting the bridge and eepro100 up with 32-bit IO addresses which
  correspond to the host MMIO region, it works perfectly.

It appears that the first bridge converts the mmio access into a PCI
IO read/write cycle without any address translation.  So, when I
access mmio 0x90011000, it would appear to cause a PCI IO cycle at
the same address.

The MMIO region for this bus is 0x90010000 - 0x9001ffff, so its impossible
to test the effect of different upper 16-bits.

I suppose I could waste some time by getting Linux to generate lots of IO
cycles and scoping the PCI bus lines to find the PCI address, but I think
its rather academic in light of the above.

--
Russell King (rmk@arm.linux.org.uk)                The developer of ARM Linux
             http://www.arm.linux.org.uk/personal/aboutme.html

Re: [PATCH] PCI updates - 32-bit IO support

[Ivan Kokshaysky]

On Thu, Dec 20, 2001 at 09:37:10AM +0000, Russell King wrote:
> - setting the bridge and eepro100 up with 32-bit IO addresses which
>   correspond to the host MMIO region, it works perfectly.

Note that this wouldn't work with DEC 2105x PCI-PCI bridges, which
support only 16 bit I/O forwarding.
However, the patch is totally harmless for architectures limiting
I/O to 64K.

Ivan.