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Thu, 19 Jun 2025 02:00:07 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20250611061609.15527-1-john.madieu.xa@bp.renesas.com> <20250611061609.15527-4-john.madieu.xa@bp.renesas.com> In-Reply-To: <20250611061609.15527-4-john.madieu.xa@bp.renesas.com> From: "Lad, Prabhakar" Date: Thu, 19 Jun 2025 09:59:41 +0100 X-Gm-Features: Ac12FXxEbSDhRUhp-8lwipAqXbd42CO72LWVe4CbodNCzZQmHjti3RncJNUk7JY Message-ID: Subject: Re: [PATCH v2 3/3] arm64: dts: renesas: rzg3e-smarc-som: Enable eth{0-1} (GBETH) interfaces To: John Madieu Cc: andrew+netdev@lunn.ch, conor+dt@kernel.org, davem@davemloft.net, edumazet@google.com, geert+renesas@glider.be, krzk+dt@kernel.org, kuba@kernel.org, pabeni@redhat.com, prabhakar.mahadev-lad.rj@bp.renesas.com, robh@kernel.org, biju.das.jz@bp.renesas.com, devicetree@vger.kernel.org, john.madieu@gmail.com, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, magnus.damm@gmail.com, netdev@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi John, Thank you for the patch. On Wed, Jun 11, 2025 at 7:20=E2=80=AFAM John Madieu wrote: > > Enable the Gigabit Ethernet Interfaces (GBETH) populated on the RZ/G3E SM= ARC EVK > > Reviewed-by: Biju Das > Tested-by: Biju Das > Signed-off-by: John Madieu > --- > .../boot/dts/renesas/rzg3e-smarc-som.dtsi | 106 ++++++++++++++++++ > 1 file changed, 106 insertions(+) > > diff --git a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi b/arch/arm6= 4/boot/dts/renesas/rzg3e-smarc-som.dtsi > index f99a09d04ddd..4b4c7f3381ad 100644 > --- a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi > +++ b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi > @@ -26,6 +26,8 @@ / { > compatible =3D "renesas,rzg3e-smarcm", "renesas,r9a09g047e57", "r= enesas,r9a09g047"; > > aliases { > + ethernet0 =3D ð0; > + ethernet1 =3D ð1; > i2c2 =3D &i2c2; > mmc0 =3D &sdhi0; > mmc2 =3D &sdhi2; > @@ -77,6 +79,74 @@ &audio_extal_clk { > clock-frequency =3D <48000000>; > }; > > +ð0 { > + phy-handle =3D <&phy0>; > + phy-mode =3D "rgmii-id"; > + > + pinctrl-0 =3D <ð0_pins>; > + pinctrl-names =3D "default"; > + status =3D "okay"; > + > + mdio { > + #address-cells =3D <1>; > + #size-cells =3D <0>; > + compatible =3D "snps,dwmac-mdio"; > + > + phy0: ethernet-phy@7 { > + compatible =3D "ethernet-phy-id0022.1640", > + "ethernet-phy-ieee802.3-c22"; > + reg =3D <7>; > + interrupts-extended =3D <&icu 3 IRQ_TYPE_LEVEL_LO= W>; > + rxc-skew-psec =3D <1400>; > + txc-skew-psec =3D <1400>; > + rxdv-skew-psec =3D <0>; > + txdv-skew-psec =3D <0>; > + rxd0-skew-psec =3D <0>; > + rxd1-skew-psec =3D <0>; > + rxd2-skew-psec =3D <0>; > + rxd3-skew-psec =3D <0>; > + txd0-skew-psec =3D <0>; > + txd1-skew-psec =3D <0>; > + txd2-skew-psec =3D <0>; > + txd3-skew-psec =3D <0>; > + }; > + }; > +}; > + > +ð1 { > + phy-handle =3D <&phy1>; > + phy-mode =3D "rgmii-id"; > + > + pinctrl-0 =3D <ð1_pins>; > + pinctrl-names =3D "default"; > + status =3D "okay"; > + > + mdio { > + #address-cells =3D <1>; > + #size-cells =3D <0>; > + compatible =3D "snps,dwmac-mdio"; > + > + phy1: ethernet-phy@7 { > + compatible =3D "ethernet-phy-id0022.1640", > + "ethernet-phy-ieee802.3-c22"; > + reg =3D <7>; > + interrupts-extended =3D <&icu 16 IRQ_TYPE_LEVEL_L= OW>; > + rxc-skew-psec =3D <1400>; > + txc-skew-psec =3D <1400>; > + rxdv-skew-psec =3D <0>; > + txdv-skew-psec =3D <0>; > + rxd0-skew-psec =3D <0>; > + rxd1-skew-psec =3D <0>; > + rxd2-skew-psec =3D <0>; > + rxd3-skew-psec =3D <0>; > + txd0-skew-psec =3D <0>; > + txd1-skew-psec =3D <0>; > + txd2-skew-psec =3D <0>; > + txd3-skew-psec =3D <0>; > + }; > + }; > +}; > + > &gpu { > status =3D "okay"; > mali-supply =3D <®_vdd0p8v_others>; > @@ -103,6 +173,42 @@ raa215300: pmic@12 { > }; > > &pinctrl { > + eth0_pins: eth0 { > + pinmux =3D , /* MDC */ > + , /* MDIO */ > + , /* PHY_INTR (IRQ2= ) */ > + , /* RXD3 */ > + , /* RXD2 */ > + , /* RXD1 */ > + , /* RXD0 */ > + , /* RXC */ > + , /* RX_CTL */ > + , /* TXD3 */ > + , /* TXD2 */ > + , /* TXD1 */ > + , /* TXD0 */ > + , /* TXC */ > + ; /* TX_CTL */ like RZ/V2H on RZ/G3E PFC_OEN BITS(0,1) need to be configured based on RGMII/MII mode? Cheers, Prabhakar > + }; > + > + eth1_pins: eth1 { > + pinmux =3D , /* MDC */ > + , /* MDIO */ > + , /* PHY_INTR (IRQ1= 5) */ > + , /* RXD3 */ > + , /* RXD2 */ > + , /* RXD1 */ > + , /* RXD0 */ > + , /* RXC */ > + , /* RX_CTL */ > + , /* TXD3 */ > + , /* TXD2 */ > + , /* TXD1 */ > + , /* TXD0 */ > + , /* TXC */ > + ; /* TX_CTL */ > + }; > + > i2c2_pins: i2c { > pinmux =3D , /* SCL2 */ > ; /* SDA2 */ > -- > 2.25.1 > >