[PATCH 0/3] clk: renesas: Add SDHI and RIIC clock support for RZ/T2H and RZ/N2H

[PATCH 0/3] clk: renesas: Add SDHI and RIIC clock support for RZ/T2H and RZ/N2H

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Hi All,

This patch series adds clock support for SDHI and RIIC peripherals on
the Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs. It introduces
the necessary clock ID definitions and updates the R9A09G077 clock driver
to support the relevant clock sources and module clocks.

Cheers,
Prabhakar

Lad Prabhakar (3):
  dt-bindings: clock: renesas,r9a09g077/87: Add SDHI_CLKHS clock ID
  clk: renesas: r9a09g077-cpg: Add PLL2 and SDHI clock support
  clk: renesas: r9a09g077-cpg: Add RIIC module clocks

 drivers/clk/renesas/r9a09g077-cpg.c               | 15 ++++++++++++++-
 .../clock/renesas,r9a09g077-cpg-mssr.h            |  1 +
 .../clock/renesas,r9a09g087-cpg-mssr.h            |  1 +
 3 files changed, 16 insertions(+), 1 deletion(-)

-- 
2.49.0

[PATCH 1/3] dt-bindings: clock: renesas,r9a09g077/87: Add SDHI_CLKHS clock ID

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Add the SDHI high-speed clock (SDHI_CLKHS) definition for the Renesas
RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs. SDHI_CLKHS is used as
a core clock for the SDHI IP and operates at 800MHz.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h | 1 +
 include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h | 1 +
 2 files changed, 2 insertions(+)

diff --git a/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h b/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h
index f6e5f62b07c4..7ecc4f0b235a 100644
--- a/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h
+++ b/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h
@@ -24,5 +24,6 @@
 #define R9A09G077_CLK_PCLKH		12
 #define R9A09G077_CLK_PCLKM		13
 #define R9A09G077_CLK_PCLKL		14
+#define R9A09G077_SDHI_CLKHS		15
 
 #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__ */
diff --git a/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h b/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h
index f28166d6015f..925e57703925 100644
--- a/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h
+++ b/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h
@@ -24,5 +24,6 @@
 #define R9A09G087_CLK_PCLKH		12
 #define R9A09G087_CLK_PCLKM		13
 #define R9A09G087_CLK_PCLKL		14
+#define R9A09G087_SDHI_CLKHS		15
 
 #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G087_CPG_H__ */
-- 
2.49.0

[PATCH 2/3] clk: renesas: r9a09g077-cpg: Add PLL2 and SDHI clock support

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Add support for PLL2 to the R9A09G077 (RZ/T2H) clock definitions and
register it as the source for the high-speed SDHI clock (SDHI_CLKHS)
operating at 800MHz.

Also add fixed-factor clock PCLKAM derived from CLK_PLL4D1, and define
module clocks for SDHI0 and SDHI1, both of which use PCLKAM as their
clock source.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/clk/renesas/r9a09g077-cpg.c | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/renesas/r9a09g077-cpg.c b/drivers/clk/renesas/r9a09g077-cpg.c
index baf917ff4beb..93862d84f95f 100644
--- a/drivers/clk/renesas/r9a09g077-cpg.c
+++ b/drivers/clk/renesas/r9a09g077-cpg.c
@@ -67,7 +67,7 @@ enum rzt2h_clk_types {
 
 enum clk_ids {
 	/* Core Clock Outputs exported to DT */
-	LAST_DT_CORE_CLK = R9A09G077_CLK_PCLKL,
+	LAST_DT_CORE_CLK = R9A09G077_SDHI_CLKHS,
 
 	/* External Input Clocks */
 	CLK_EXTAL,
@@ -76,9 +76,11 @@ enum clk_ids {
 	CLK_LOCO,
 	CLK_PLL0,
 	CLK_PLL1,
+	CLK_PLL2,
 	CLK_PLL4,
 	CLK_SEL_CLK_PLL0,
 	CLK_SEL_CLK_PLL1,
+	CLK_SEL_CLK_PLL2,
 	CLK_SEL_CLK_PLL4,
 	CLK_PLL4D1,
 	CLK_SCI0ASYNC,
@@ -105,6 +107,7 @@ static const struct clk_div_table dtable_24_25_30_32[] = {
 
 static const char * const sel_clk_pll0[] = { ".loco", ".pll0" };
 static const char * const sel_clk_pll1[] = { ".loco", ".pll1" };
+static const char * const sel_clk_pll2[] = { ".loco", ".pll2" };
 static const char * const sel_clk_pll4[] = { ".loco", ".pll4" };
 
 static const struct cpg_core_clk r9a09g077_core_clks[] __initconst = {
@@ -115,12 +118,15 @@ static const struct cpg_core_clk r9a09g077_core_clks[] __initconst = {
 	DEF_RATE(".loco", CLK_LOCO, 1000 * 1000),
 	DEF_FIXED(".pll0", CLK_PLL0, CLK_EXTAL, 1, 48),
 	DEF_FIXED(".pll1", CLK_PLL1, CLK_EXTAL, 1, 40),
+	DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 1, 32),
 	DEF_FIXED(".pll4", CLK_PLL4, CLK_EXTAL, 1, 96),
 
 	DEF_MUX(".sel_clk_pll0", CLK_SEL_CLK_PLL0, SEL_PLL,
 		sel_clk_pll0, ARRAY_SIZE(sel_clk_pll0), CLK_MUX_READ_ONLY),
 	DEF_MUX(".sel_clk_pll1", CLK_SEL_CLK_PLL1, SEL_PLL,
 		sel_clk_pll1, ARRAY_SIZE(sel_clk_pll1), CLK_MUX_READ_ONLY),
+	DEF_MUX(".sel_clk_pll2", CLK_SEL_CLK_PLL2, SEL_PLL,
+		sel_clk_pll2, ARRAY_SIZE(sel_clk_pll2), CLK_MUX_READ_ONLY),
 	DEF_MUX(".sel_clk_pll4", CLK_SEL_CLK_PLL4, SEL_PLL,
 		sel_clk_pll4, ARRAY_SIZE(sel_clk_pll4), CLK_MUX_READ_ONLY),
 
@@ -142,10 +148,14 @@ static const struct cpg_core_clk r9a09g077_core_clks[] __initconst = {
 	DEF_FIXED("PCLKGPTL", R9A09G077_CLK_PCLKGPTL, CLK_SEL_CLK_PLL1, 2, 1),
 	DEF_FIXED("PCLKM", R9A09G077_CLK_PCLKM, CLK_SEL_CLK_PLL1, 8, 1),
 	DEF_FIXED("PCLKL", R9A09G077_CLK_PCLKL, CLK_SEL_CLK_PLL1, 16, 1),
+	DEF_FIXED("PCLKAM", R9A09G077_CLK_PCLKAM, CLK_PLL4D1, 12, 1),
+	DEF_FIXED("SDHI_CLKHS", R9A09G077_SDHI_CLKHS, CLK_SEL_CLK_PLL2, 1, 1),
 };
 
 static const struct mssr_mod_clk r9a09g077_mod_clks[] __initconst = {
 	DEF_MOD("sci0fck", 8, CLK_SCI0ASYNC),
+	DEF_MOD("sdhi0", 1212, R9A09G077_CLK_PCLKAM),
+	DEF_MOD("sdhi1", 1213, R9A09G077_CLK_PCLKAM),
 };
 
 static struct clk * __init
-- 
2.49.0

[PATCH 3/3] clk: renesas: r9a09g077-cpg: Add RIIC module clocks

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Add RIIC module clocks for: iic0, iic1, and iic2.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/clk/renesas/r9a09g077-cpg.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/clk/renesas/r9a09g077-cpg.c b/drivers/clk/renesas/r9a09g077-cpg.c
index 93862d84f95f..ed1e94cbd267 100644
--- a/drivers/clk/renesas/r9a09g077-cpg.c
+++ b/drivers/clk/renesas/r9a09g077-cpg.c
@@ -154,6 +154,9 @@ static const struct cpg_core_clk r9a09g077_core_clks[] __initconst = {
 
 static const struct mssr_mod_clk r9a09g077_mod_clks[] __initconst = {
 	DEF_MOD("sci0fck", 8, CLK_SCI0ASYNC),
+	DEF_MOD("iic0", 100, R9A09G077_CLK_PCLKL),
+	DEF_MOD("iic1", 101, R9A09G077_CLK_PCLKL),
+	DEF_MOD("iic2", 501, R9A09G077_CLK_PCLKL),
 	DEF_MOD("sdhi0", 1212, R9A09G077_CLK_PCLKAM),
 	DEF_MOD("sdhi1", 1213, R9A09G077_CLK_PCLKAM),
 };
-- 
2.49.0

Re: [PATCH 1/3] dt-bindings: clock: renesas,r9a09g077/87: Add SDHI_CLKHS clock ID

[Geert Uytterhoeven]

Hi Prabhakar,

On Wed, 25 Jun 2025 at 16:17, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Add the SDHI high-speed clock (SDHI_CLKHS) definition for the Renesas
> RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs. SDHI_CLKHS is used as
> a core clock for the SDHI IP and operates at 800MHz.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Thanks for your patch!

>  include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h | 1 +
>  include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h | 1 +

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will split, and queue in renesas-r9a09g077-dt-binding-defs resp.
renesas-r9a09g087-dt-binding-defs, to be shared by renesas-clk and
renesas-devel.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 2/3] clk: renesas: r9a09g077-cpg: Add PLL2 and SDHI clock support

[Geert Uytterhoeven]

On Wed, 25 Jun 2025 at 16:17, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Add support for PLL2 to the R9A09G077 (RZ/T2H) clock definitions and
> register it as the source for the high-speed SDHI clock (SDHI_CLKHS)
> operating at 800MHz.
>
> Also add fixed-factor clock PCLKAM derived from CLK_PLL4D1, and define
> module clocks for SDHI0 and SDHI1, both of which use PCLKAM as their
> clock source.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-clk for v6.17.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 3/3] clk: renesas: r9a09g077-cpg: Add RIIC module clocks

[Geert Uytterhoeven]

Hi Prabhakar,

On Wed, 25 Jun 2025 at 16:17, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Add RIIC module clocks for: iic0, iic1, and iic2.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Thanks for your patch!

> --- a/drivers/clk/renesas/r9a09g077-cpg.c
> +++ b/drivers/clk/renesas/r9a09g077-cpg.c
> @@ -154,6 +154,9 @@ static const struct cpg_core_clk r9a09g077_core_clks[] __initconst = {
>
>  static const struct mssr_mod_clk r9a09g077_mod_clks[] __initconst = {
>         DEF_MOD("sci0fck", 8, CLK_SCI0ASYNC),
> +       DEF_MOD("iic0", 100, R9A09G077_CLK_PCLKL),
> +       DEF_MOD("iic1", 101, R9A09G077_CLK_PCLKL),
> +       DEF_MOD("iic2", 501, R9A09G077_CLK_PCLKL),

Shouldn't that be 601?
(MSTPCRA => xx, MSTPCRB => 1xx, MSTPCRG => 6xx)
If you agree, I can fix that while applying...

>         DEF_MOD("sdhi0", 1212, R9A09G077_CLK_PCLKAM),
>         DEF_MOD("sdhi1", 1213, R9A09G077_CLK_PCLKAM),
>  };

The rest LGTM, so with the above fixed:
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 1/3] dt-bindings: clock: renesas,r9a09g077/87: Add SDHI_CLKHS clock ID

[Geert Uytterhoeven]

On Wed, 2 Jul 2025 at 15:37, Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> On Wed, 25 Jun 2025 at 16:17, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Add the SDHI high-speed clock (SDHI_CLKHS) definition for the Renesas
> > RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs. SDHI_CLKHS is used as
> > a core clock for the SDHI IP and operates at 800MHz.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Thanks for your patch!
>
> >  include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h | 1 +
> >  include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h | 1 +
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> i.e. will split, and queue in renesas-r9a09g077-dt-binding-defs resp.
> renesas-r9a09g087-dt-binding-defs, to be shared by renesas-clk and
> renesas-devel.

Looks like I can do without the split, as renesas-r9a09g087-dt-binding-defs
is based on renesas-r9a09g077-dt-binding-defs.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 1/3] dt-bindings: clock: renesas,r9a09g077/87: Add SDHI_CLKHS clock ID

[Lad, Prabhakar]

Hi Geert,

Thank you for the review.

On Wed, Jul 2, 2025 at 7:23 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> On Wed, 2 Jul 2025 at 15:37, Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > On Wed, 25 Jun 2025 at 16:17, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > >
> > > Add the SDHI high-speed clock (SDHI_CLKHS) definition for the Renesas
> > > RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs. SDHI_CLKHS is used as
> > > a core clock for the SDHI IP and operates at 800MHz.
> > >
> > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Thanks for your patch!
> >
> > >  include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h | 1 +
> > >  include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h | 1 +
> >
> > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > i.e. will split, and queue in renesas-r9a09g077-dt-binding-defs resp.
> > renesas-r9a09g087-dt-binding-defs, to be shared by renesas-clk and
> > renesas-devel.
>
> Looks like I can do without the split, as renesas-r9a09g087-dt-binding-defs
> is based on renesas-r9a09g077-dt-binding-defs.
>
Great!

I mainly did this to reduce the load on DT maintainers.

Cheers,
Prabhakar

Re: [PATCH 3/3] clk: renesas: r9a09g077-cpg: Add RIIC module clocks

[Lad, Prabhakar]

Hi Geert,

Thank you for the review.

On Wed, Jul 2, 2025 at 2:46 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Wed, 25 Jun 2025 at 16:17, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Add RIIC module clocks for: iic0, iic1, and iic2.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Thanks for your patch!
>
> > --- a/drivers/clk/renesas/r9a09g077-cpg.c
> > +++ b/drivers/clk/renesas/r9a09g077-cpg.c
> > @@ -154,6 +154,9 @@ static const struct cpg_core_clk r9a09g077_core_clks[] __initconst = {
> >
> >  static const struct mssr_mod_clk r9a09g077_mod_clks[] __initconst = {
> >         DEF_MOD("sci0fck", 8, CLK_SCI0ASYNC),
> > +       DEF_MOD("iic0", 100, R9A09G077_CLK_PCLKL),
> > +       DEF_MOD("iic1", 101, R9A09G077_CLK_PCLKL),
> > +       DEF_MOD("iic2", 501, R9A09G077_CLK_PCLKL),
>
> Shouldn't that be 601?
> (MSTPCRA => xx, MSTPCRB => 1xx, MSTPCRG => 6xx)
> If you agree, I can fix that while applying...
>
Agreed, thank you for taking care of it.

Cheers,
Prabhakar

> >         DEF_MOD("sdhi0", 1212, R9A09G077_CLK_PCLKAM),
> >         DEF_MOD("sdhi1", 1213, R9A09G077_CLK_PCLKAM),
> >  };
>
> The rest LGTM, so with the above fixed:
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>
> Gr{oetje,eeting}s,
>
>                         Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds

Re: [PATCH 3/3] clk: renesas: r9a09g077-cpg: Add RIIC module clocks

[Geert Uytterhoeven]

Hi Prabhakar,

On Wed, 2 Jul 2025 at 21:30, Lad, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> On Wed, Jul 2, 2025 at 2:46 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > On Wed, 25 Jun 2025 at 16:17, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > >
> > > Add RIIC module clocks for: iic0, iic1, and iic2.
> > >
> > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Thanks for your patch!
> >
> > > --- a/drivers/clk/renesas/r9a09g077-cpg.c
> > > +++ b/drivers/clk/renesas/r9a09g077-cpg.c
> > > @@ -154,6 +154,9 @@ static const struct cpg_core_clk r9a09g077_core_clks[] __initconst = {
> > >
> > >  static const struct mssr_mod_clk r9a09g077_mod_clks[] __initconst = {
> > >         DEF_MOD("sci0fck", 8, CLK_SCI0ASYNC),
> > > +       DEF_MOD("iic0", 100, R9A09G077_CLK_PCLKL),
> > > +       DEF_MOD("iic1", 101, R9A09G077_CLK_PCLKL),
> > > +       DEF_MOD("iic2", 501, R9A09G077_CLK_PCLKL),
> >
> > Shouldn't that be 601?
> > (MSTPCRA => xx, MSTPCRB => 1xx, MSTPCRG => 6xx)
> > If you agree, I can fix that while applying...
> >
> Agreed, thank you for taking care of it.

Thanks, queued in renesas-clk for v6.17, and pushed.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds