* [PATCH] LoongArch: BPF: Optimize sign-extention mov instructions
@ 2025-08-26 6:49 Tiezhu Yang
2025-08-27 1:27 ` Hengqi Chen
0 siblings, 1 reply; 3+ messages in thread
From: Tiezhu Yang @ 2025-08-26 6:49 UTC (permalink / raw)
To: Huacai Chen; +Cc: Hengqi Chen, bpf, loongarch, linux-kernel
For 8-bit and 16-bit sign-extention mov instructions, it can use the native
instructions ext.w.b and ext.w.h directly, no need to use the temporary t1
register, just remove the redundant operations.
Here are the test results:
# modprobe test_bpf test_range=81,84
# dmesg -t | tail -5
test_bpf: #81 ALU_MOVSX | BPF_B jited:1 5 PASS
test_bpf: #82 ALU_MOVSX | BPF_H jited:1 5 PASS
test_bpf: #83 ALU64_MOVSX | BPF_B jited:1 5 PASS
test_bpf: #84 ALU64_MOVSX | BPF_H jited:1 5 PASS
test_bpf: Summary: 4 PASSED, 0 FAILED, [4/4 JIT'ed]
Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn>
---
arch/loongarch/net/bpf_jit.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/arch/loongarch/net/bpf_jit.c b/arch/loongarch/net/bpf_jit.c
index abfdb6bb5c38..7072db18c6cd 100644
--- a/arch/loongarch/net/bpf_jit.c
+++ b/arch/loongarch/net/bpf_jit.c
@@ -527,13 +527,11 @@ static int build_insn(const struct bpf_insn *insn, struct jit_ctx *ctx, bool ext
emit_zext_32(ctx, dst, is32);
break;
case 8:
- move_reg(ctx, t1, src);
- emit_insn(ctx, extwb, dst, t1);
+ emit_insn(ctx, extwb, dst, src);
emit_zext_32(ctx, dst, is32);
break;
case 16:
- move_reg(ctx, t1, src);
- emit_insn(ctx, extwh, dst, t1);
+ emit_insn(ctx, extwh, dst, src);
emit_zext_32(ctx, dst, is32);
break;
case 32:
--
2.42.0
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH] LoongArch: BPF: Optimize sign-extention mov instructions
2025-08-26 6:49 [PATCH] LoongArch: BPF: Optimize sign-extention mov instructions Tiezhu Yang
@ 2025-08-27 1:27 ` Hengqi Chen
2025-08-27 10:18 ` Huacai Chen
0 siblings, 1 reply; 3+ messages in thread
From: Hengqi Chen @ 2025-08-27 1:27 UTC (permalink / raw)
To: Tiezhu Yang; +Cc: Huacai Chen, bpf, loongarch, linux-kernel
On Tue, Aug 26, 2025 at 2:49 PM Tiezhu Yang <yangtiezhu@loongson.cn> wrote:
>
> For 8-bit and 16-bit sign-extention mov instructions, it can use the native
> instructions ext.w.b and ext.w.h directly, no need to use the temporary t1
> register, just remove the redundant operations.
>
> Here are the test results:
>
> # modprobe test_bpf test_range=81,84
> # dmesg -t | tail -5
> test_bpf: #81 ALU_MOVSX | BPF_B jited:1 5 PASS
> test_bpf: #82 ALU_MOVSX | BPF_H jited:1 5 PASS
> test_bpf: #83 ALU64_MOVSX | BPF_B jited:1 5 PASS
> test_bpf: #84 ALU64_MOVSX | BPF_H jited:1 5 PASS
> test_bpf: Summary: 4 PASSED, 0 FAILED, [4/4 JIT'ed]
>
> Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn>
> ---
> arch/loongarch/net/bpf_jit.c | 6 ++----
> 1 file changed, 2 insertions(+), 4 deletions(-)
>
> diff --git a/arch/loongarch/net/bpf_jit.c b/arch/loongarch/net/bpf_jit.c
> index abfdb6bb5c38..7072db18c6cd 100644
> --- a/arch/loongarch/net/bpf_jit.c
> +++ b/arch/loongarch/net/bpf_jit.c
> @@ -527,13 +527,11 @@ static int build_insn(const struct bpf_insn *insn, struct jit_ctx *ctx, bool ext
> emit_zext_32(ctx, dst, is32);
> break;
> case 8:
> - move_reg(ctx, t1, src);
> - emit_insn(ctx, extwb, dst, t1);
> + emit_insn(ctx, extwb, dst, src);
> emit_zext_32(ctx, dst, is32);
> break;
> case 16:
> - move_reg(ctx, t1, src);
> - emit_insn(ctx, extwh, dst, t1);
> + emit_insn(ctx, extwh, dst, src);
> emit_zext_32(ctx, dst, is32);
> break;
> case 32:
> --
Acked-by: Hengqi Chen <hengqi.chen@gmail.com>
> 2.42.0
>
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] LoongArch: BPF: Optimize sign-extention mov instructions
2025-08-27 1:27 ` Hengqi Chen
@ 2025-08-27 10:18 ` Huacai Chen
0 siblings, 0 replies; 3+ messages in thread
From: Huacai Chen @ 2025-08-27 10:18 UTC (permalink / raw)
To: Hengqi Chen; +Cc: Tiezhu Yang, bpf, loongarch, linux-kernel
Applied, thanks.
Huacai
On Wed, Aug 27, 2025 at 9:27 AM Hengqi Chen <hengqi.chen@gmail.com> wrote:
>
> On Tue, Aug 26, 2025 at 2:49 PM Tiezhu Yang <yangtiezhu@loongson.cn> wrote:
> >
> > For 8-bit and 16-bit sign-extention mov instructions, it can use the native
> > instructions ext.w.b and ext.w.h directly, no need to use the temporary t1
> > register, just remove the redundant operations.
> >
> > Here are the test results:
> >
> > # modprobe test_bpf test_range=81,84
> > # dmesg -t | tail -5
> > test_bpf: #81 ALU_MOVSX | BPF_B jited:1 5 PASS
> > test_bpf: #82 ALU_MOVSX | BPF_H jited:1 5 PASS
> > test_bpf: #83 ALU64_MOVSX | BPF_B jited:1 5 PASS
> > test_bpf: #84 ALU64_MOVSX | BPF_H jited:1 5 PASS
> > test_bpf: Summary: 4 PASSED, 0 FAILED, [4/4 JIT'ed]
> >
> > Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn>
> > ---
> > arch/loongarch/net/bpf_jit.c | 6 ++----
> > 1 file changed, 2 insertions(+), 4 deletions(-)
> >
> > diff --git a/arch/loongarch/net/bpf_jit.c b/arch/loongarch/net/bpf_jit.c
> > index abfdb6bb5c38..7072db18c6cd 100644
> > --- a/arch/loongarch/net/bpf_jit.c
> > +++ b/arch/loongarch/net/bpf_jit.c
> > @@ -527,13 +527,11 @@ static int build_insn(const struct bpf_insn *insn, struct jit_ctx *ctx, bool ext
> > emit_zext_32(ctx, dst, is32);
> > break;
> > case 8:
> > - move_reg(ctx, t1, src);
> > - emit_insn(ctx, extwb, dst, t1);
> > + emit_insn(ctx, extwb, dst, src);
> > emit_zext_32(ctx, dst, is32);
> > break;
> > case 16:
> > - move_reg(ctx, t1, src);
> > - emit_insn(ctx, extwh, dst, t1);
> > + emit_insn(ctx, extwh, dst, src);
> > emit_zext_32(ctx, dst, is32);
> > break;
> > case 32:
> > --
>
> Acked-by: Hengqi Chen <hengqi.chen@gmail.com>
>
> > 2.42.0
> >
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2025-08-27 10:18 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz follow: Atom feed
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2025-08-26 6:49 [PATCH] LoongArch: BPF: Optimize sign-extention mov instructions Tiezhu Yang
2025-08-27 1:27 ` Hengqi Chen
2025-08-27 10:18 ` Huacai Chen
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