From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752553AbcJJIAB (ORCPT ); Mon, 10 Oct 2016 04:00:01 -0400 Received: from mail-oi0-f42.google.com ([209.85.218.42]:33129 "EHLO mail-oi0-f42.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752266AbcJJH77 (ORCPT ); Mon, 10 Oct 2016 03:59:59 -0400 MIME-Version: 1.0 In-Reply-To: References: From: Linus Walleij Date: Mon, 10 Oct 2016 09:59:57 +0200 Message-ID: Subject: Re: [PATCH 0/8] pinctrl: aspeed: Fixes for core and g5, implement remaining pins To: Andrew Jeffery Cc: Joel Stanley , Mark Rutland , Rob Herring , "linux-gpio@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "devicetree@vger.kernel.org" , openbmc@lists.ozlabs.org Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Sep 27, 2016 at 4:50 PM, Andrew Jeffery wrote: > The initial Aspeed pinctrl patches implemented a subset of pins for each of the > g4 and g5 SoCs. This series provides a number of fixes to the initial patches, > mostly for issues identified in the g5 driver. The fixes account for the first > half of the series (up to and including "pinctrl: aspeed-g5: Fix pin > association of SPI1 function") and should be applied for 4.9. Those are applied for fixes. > The second half, from "pinctrl: aspeed: Enable capture of off-SCU pinmux > state", implements some additional functionality in the core engine for the > Aspeed SoCs and follows up with patches implementing mux configuration tables > for all remaining pins. Given the significant additions in the last few > patches, their lateness in the cycle and the light testing they have received > they are best left for 4.10, but I'm keen to get them out for review. I'm holding these back until v4.9-rc1 is out. Yours, Linus Walleij