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AJvYcCXpjtlWr5ylb1tNT49IXhecR6N/tJqCY+Az95oAV82Ksc9/Mv1jwaRZcswlb6krHBIP1DDRJVo=@vger.kernel.org X-Gm-Message-State: AOJu0YzrEjTrVHconPndsOBaAI+0vqqKGwvv3RV/qyc6lzZFptZAzXW4 i2BRHq6Ztio2xnWXYNedbA63ozy4YsXaeNNgdcnq1IX+bm3FBdkQtTRBy7KskOTSRbCPImI/sv5 iqQj84Cf1S+HPUuGlpP3kyQsFhW0= X-Gm-Gg: ASbGncvC2MTjQUqT4QJoEdiiFfUsazo8V34wZt8Kuw5aKMz1EHPNVEpnOCergv6ThHf v9/orKlyz2ZV4BAtwHZ1gmSRSVdK6W+FRqFfewItomaaiHcyLiQxfuJ3sMG+0dfh9rCpH3zGBMd 6o1xg9JwfI27znnVpDSLzowA== X-Google-Smtp-Source: AGHT+IGoR/1KNKu8t6FhcfkvG15adjneHBLuPet1jUD8RK6gXmMHJVwSbb0sxCBa3iS20c2BjnGa1dBq89e+BFUlqs0= X-Received: by 2002:a17:902:e552:b0:223:5124:ee7f with SMTP id d9443c01a7336-22e103876aemr96861115ad.12.1746543927415; Tue, 06 May 2025 08:05:27 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20250505221419.2672473-1-sashal@kernel.org> <20250505221419.2672473-248-sashal@kernel.org> In-Reply-To: <20250505221419.2672473-248-sashal@kernel.org> From: Alex Deucher Date: Tue, 6 May 2025 11:05:15 -0400 X-Gm-Features: ATxdqUG9foOxWfXm1xZFyjnjBCiu9l7qR46nlmJ4liwGbAsOLlF1aF7W238Y4Mg Message-ID: Subject: Re: [PATCH AUTOSEL 6.14 248/642] drm/amdgpu: add dce_v6_0_soft_reset() to DCE6 To: Sasha Levin Cc: linux-kernel@vger.kernel.org, stable@vger.kernel.org, Alexandre Demers , Alex Deucher , christian.koenig@amd.com, airlied@gmail.com, simona@ffwll.ch, sunil.khatri@amd.com, boyuan.zhang@amd.com, amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Mon, May 5, 2025 at 6:24=E2=80=AFPM Sasha Levin wrot= e: > > From: Alexandre Demers > > [ Upstream commit ab23db6d08efdda5d13d01a66c593d0e57f8917f ] > > DCE6 was missing soft reset, but it was easily identifiable under radeon. > This should be it, pretty much as it is done under DCE8 and DCE10. > > Signed-off-by: Alexandre Demers > Signed-off-by: Alex Deucher > Signed-off-by: Sasha Levin This is not stable material. Alex > --- > drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 53 ++++++++++++++++++++++++++- > 1 file changed, 51 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/= amdgpu/dce_v6_0.c > index 915804a6a1d7d..ed5e06b677df1 100644 > --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c > @@ -370,13 +370,41 @@ static u32 dce_v6_0_hpd_get_gpio_reg(struct amdgpu_= device *adev) > return mmDC_GPIO_HPD_A; > } > > +static bool dce_v6_0_is_display_hung(struct amdgpu_device *adev) > +{ > + u32 crtc_hung =3D 0; > + u32 crtc_status[6]; > + u32 i, j, tmp; > + > + for (i =3D 0; i < adev->mode_info.num_crtc; i++) { > + if (RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & CRTC_CONTR= OL__CRTC_MASTER_EN_MASK) { > + crtc_status[i] =3D RREG32(mmCRTC_STATUS_HV_COUNT = + crtc_offsets[i]); > + crtc_hung |=3D (1 << i); > + } > + } > + > + for (j =3D 0; j < 10; j++) { > + for (i =3D 0; i < adev->mode_info.num_crtc; i++) { > + if (crtc_hung & (1 << i)) { > + tmp =3D RREG32(mmCRTC_STATUS_HV_COUNT + c= rtc_offsets[i]); > + if (tmp !=3D crtc_status[i]) > + crtc_hung &=3D ~(1 << i); > + } > + } > + if (crtc_hung =3D=3D 0) > + return false; > + udelay(100); > + } > + > + return true; > +} > + > static void dce_v6_0_set_vga_render_state(struct amdgpu_device *adev, > bool render) > { > if (!render) > WREG32(mmVGA_RENDER_CONTROL, > RREG32(mmVGA_RENDER_CONTROL) & VGA_VSTATUS_CNTL); > - > } > > static int dce_v6_0_get_num_crtc(struct amdgpu_device *adev) > @@ -2872,7 +2900,28 @@ static bool dce_v6_0_is_idle(void *handle) > > static int dce_v6_0_soft_reset(struct amdgpu_ip_block *ip_block) > { > - DRM_INFO("xxxx: dce_v6_0_soft_reset --- no impl!!\n"); > + u32 srbm_soft_reset =3D 0, tmp; > + struct amdgpu_device *adev =3D ip_block->adev; > + > + if (dce_v6_0_is_display_hung(adev)) > + srbm_soft_reset |=3D SRBM_SOFT_RESET__SOFT_RESET_DC_MASK; > + > + if (srbm_soft_reset) { > + tmp =3D RREG32(mmSRBM_SOFT_RESET); > + tmp |=3D srbm_soft_reset; > + dev_info(adev->dev, "SRBM_SOFT_RESET=3D0x%08X\n", tmp); > + WREG32(mmSRBM_SOFT_RESET, tmp); > + tmp =3D RREG32(mmSRBM_SOFT_RESET); > + > + udelay(50); > + > + tmp &=3D ~srbm_soft_reset; > + WREG32(mmSRBM_SOFT_RESET, tmp); > + tmp =3D RREG32(mmSRBM_SOFT_RESET); > + > + /* Wait a little for things to settle down */ > + udelay(50); > + } > return 0; > } > > -- > 2.39.5 >