From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753091AbcAOE4x (ORCPT ); Thu, 14 Jan 2016 23:56:53 -0500 Received: from mail-io0-f194.google.com ([209.85.223.194]:35778 "EHLO mail-io0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751998AbcAOE4v (ORCPT ); Thu, 14 Jan 2016 23:56:51 -0500 MIME-Version: 1.0 In-Reply-To: <20160115024534.GB29132@Asurada-Nvidia> References: <1452788982-11583-1-git-send-email-caleb@crome.org> <20160114201858.GA17567@Asurada-Nvidia> <20160115024534.GB29132@Asurada-Nvidia> From: Caleb Crome Date: Thu, 14 Jan 2016 20:56:31 -0800 Message-ID: Subject: Re: [PATCH RFC 1/1] ASoC: fsl_ssi: Make fifo watermark and maxburst settings device tree options To: Nicolin Chen Cc: Timur Tabi , Xiubo Li , Liam Girdwood , Mark Brown , Jaroslav Kysela , Takashi Iwai , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, "alsa-devel@alsa-project.org" Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Jan 14, 2016 at 6:45 PM, Nicolin Chen wrote: > On Thu, Jan 14, 2016 at 01:26:24PM -0800, Caleb Crome wrote: > >> As for optimal settings, I finally came to a setting of 4 for depth & >> maxburst, which will result in more DMA requests, but it's the only >> way that works at 48kHz for me. The default settings is 13 (15 - 2) >> for the ones of the 15 item fifo, which is a pretty dramatic >> difference. I just don't know if other chips will behave badly in >> that case. > > What's your final configuration for TFWM0 bits, 4? Yes, a value of 4 for my use case: i.MX6 @ 768000 words/second (48khz * 16 channels). Also, works at 8kHz, 16kHz 32 kHz. A setting of 8 does not work reliably at 48kHz but does work at 8, 16 and 32. -caleb