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Mon, 14 Jul 2025 22:26:41 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20250624143220.244549-1-laura.nao@collabora.com> <20250624143220.244549-13-laura.nao@collabora.com> In-Reply-To: <20250624143220.244549-13-laura.nao@collabora.com> From: Chen-Yu Tsai Date: Tue, 15 Jul 2025 13:26:30 +0800 X-Gm-Features: Ac12FXx0XfJFXA_DIIE4IblGQiwtiWyeXBGiD295gCS64kpCUO8jzl3QeCZ10ZM Message-ID: Subject: Re: [PATCH v2 12/29] clk: mediatek: Add MT8196 topckgen clock support To: Laura Nao Cc: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, p.zabel@pengutronix.de, richardcochran@gmail.com, guangjie.song@mediatek.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, netdev@vger.kernel.org, kernel@collabora.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Another thing, On Tue, Jun 24, 2025 at 10:33=E2=80=AFPM Laura Nao wrote: > > Add support for the MT8196 topckgen clock controller, which provides > muxes and dividers for clock selection in other IP blocks. > > Reviewed-by: AngeloGioacchino Del Regno > Signed-off-by: Laura Nao > --- > drivers/clk/mediatek/Makefile | 2 +- > drivers/clk/mediatek/clk-mt8196-topckgen.c | 1257 ++++++++++++++++++++ > 2 files changed, 1258 insertions(+), 1 deletion(-) > create mode 100644 drivers/clk/mediatek/clk-mt8196-topckgen.c > > diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefil= e > index b1773d2bcb3d..bc0e86e20074 100644 > --- a/drivers/clk/mediatek/Makefile > +++ b/drivers/clk/mediatek/Makefile > @@ -160,7 +160,7 @@ obj-$(CONFIG_COMMON_CLK_MT8195_VDOSYS) +=3D clk-mt819= 5-vdo0.o clk-mt8195-vdo1.o > obj-$(CONFIG_COMMON_CLK_MT8195_VENCSYS) +=3D clk-mt8195-venc.o > obj-$(CONFIG_COMMON_CLK_MT8195_VPPSYS) +=3D clk-mt8195-vpp0.o clk-mt8195= -vpp1.o > obj-$(CONFIG_COMMON_CLK_MT8195_WPESYS) +=3D clk-mt8195-wpe.o > -obj-$(CONFIG_COMMON_CLK_MT8196) +=3D clk-mt8196-apmixedsys.o > +obj-$(CONFIG_COMMON_CLK_MT8196) +=3D clk-mt8196-apmixedsys.o clk-mt8196-= topckgen.o > obj-$(CONFIG_COMMON_CLK_MT8365) +=3D clk-mt8365-apmixedsys.o clk-mt8365.= o > obj-$(CONFIG_COMMON_CLK_MT8365_APU) +=3D clk-mt8365-apu.o > obj-$(CONFIG_COMMON_CLK_MT8365_CAM) +=3D clk-mt8365-cam.o > diff --git a/drivers/clk/mediatek/clk-mt8196-topckgen.c b/drivers/clk/med= iatek/clk-mt8196-topckgen.c > new file mode 100644 > index 000000000000..fc0c1227dd8d > --- /dev/null > +++ b/drivers/clk/mediatek/clk-mt8196-topckgen.c [...] > + FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "vlp_apll1", 1, 4), > + FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "vlp_apll1", 1, 8), > + FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "vlp_apll2", 1, 4), > + FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "vlp_apll2", 1, 8), These aren't used anywhere in this driver, but they are referenced directly in the vlpckgen driver. Maybe these should be moved over to that driver instead? Otherwise we end up with some weird circular link between the two clock controllers which doesn't seem correct to me. [...]