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From: Chen-Yu Tsai <wenst@chromium.org>
To: Laura Nao <laura.nao@collabora.com>
Cc: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org,
	krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com,
	angelogioacchino.delregno@collabora.com, p.zabel@pengutronix.de,
	richardcochran@gmail.com, guangjie.song@mediatek.com,
	linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-mediatek@lists.infradead.org, netdev@vger.kernel.org,
	kernel@collabora.com,
	"Nícolas F . R . A . Prado" <nfraprado@collabora.com>
Subject: Re: [PATCH v4 06/27] clk: mediatek: clk-gate: Refactor mtk_clk_register_gate to use mtk_gate struct
Date: Fri, 15 Aug 2025 12:42:06 +0900	[thread overview]
Message-ID: <CAGXv+5GxJs03EcMt0jm-x_fDuy_RtCrnOmyJvVVgAP9O9R6E2Q@mail.gmail.com> (raw)
In-Reply-To: <20250805135447.149231-7-laura.nao@collabora.com>

On Tue, Aug 5, 2025 at 10:55 PM Laura Nao <laura.nao@collabora.com> wrote:
>
> MT8196 uses a HW voter for gate enable/disable control, with
> set/clr/sta registers located in a separate regmap. Refactor
> mtk_clk_register_gate() to take a struct mtk_gate instead of individual
> parameters, avoiding the need to add three extra arguments to support
> HW voter register offsets.
>
> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> Signed-off-by: Laura Nao <laura.nao@collabora.com>
> ---
>  drivers/clk/mediatek/clk-gate.c | 35 ++++++++++++---------------------
>  1 file changed, 13 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/clk/mediatek/clk-gate.c b/drivers/clk/mediatek/clk-gate.c
> index 67d9e741c5e7..0375ccad4be3 100644
> --- a/drivers/clk/mediatek/clk-gate.c
> +++ b/drivers/clk/mediatek/clk-gate.c
> @@ -152,12 +152,9 @@ const struct clk_ops mtk_clk_gate_ops_no_setclr_inv = {
>  };
>  EXPORT_SYMBOL_GPL(mtk_clk_gate_ops_no_setclr_inv);
>
> -static struct clk_hw *mtk_clk_register_gate(struct device *dev, const char *name,
> -                                        const char *parent_name,
> -                                        struct regmap *regmap, int set_ofs,
> -                                        int clr_ofs, int sta_ofs, u8 bit,
> -                                        const struct clk_ops *ops,
> -                                        unsigned long flags)
> +static struct clk_hw *mtk_clk_register_gate(struct device *dev,
> +                                               const struct mtk_gate *gate,
> +                                               struct regmap *regmap)
>  {
>         struct mtk_clk_gate *cg;
>         int ret;
> @@ -167,17 +164,17 @@ static struct clk_hw *mtk_clk_register_gate(struct device *dev, const char *name
>         if (!cg)
>                 return ERR_PTR(-ENOMEM);
>
> -       init.name = name;
> -       init.flags = flags | CLK_SET_RATE_PARENT;
> -       init.parent_names = parent_name ? &parent_name : NULL;
> -       init.num_parents = parent_name ? 1 : 0;
> -       init.ops = ops;
> +       init.name = gate->name;
> +       init.flags = gate->flags | CLK_SET_RATE_PARENT;
> +       init.parent_names = gate->parent_name ? &gate->parent_name : NULL;
> +       init.num_parents = gate->parent_name ? 1 : 0;
> +       init.ops = gate->ops;
>
>         cg->regmap = regmap;
> -       cg->set_ofs = set_ofs;
> -       cg->clr_ofs = clr_ofs;
> -       cg->sta_ofs = sta_ofs;
> -       cg->bit = bit;
> +       cg->set_ofs = gate->regs->set_ofs;
> +       cg->clr_ofs = gate->regs->clr_ofs;
> +       cg->sta_ofs = gate->regs->sta_ofs;
> +       cg->bit = gate->shift;

I'd rather see |struct mtk_clk_gate| (the runtime data) gain a pointer
to the static data |struct mtk_gate| instead of doing all the copying.
This is just needless duplication.

ChenYu

>         cg->hw.init = &init;
>
> @@ -228,13 +225,7 @@ int mtk_clk_register_gates(struct device *dev, struct device_node *node,
>                         continue;
>                 }
>
> -               hw = mtk_clk_register_gate(dev, gate->name, gate->parent_name,
> -                                           regmap,
> -                                           gate->regs->set_ofs,
> -                                           gate->regs->clr_ofs,
> -                                           gate->regs->sta_ofs,
> -                                           gate->shift, gate->ops,
> -                                           gate->flags);
> +               hw = mtk_clk_register_gate(dev, gate, regmap);
>
>                 if (IS_ERR(hw)) {
>                         pr_err("Failed to register clk %s: %pe\n", gate->name,
> --
> 2.39.5
>

  reply	other threads:[~2025-08-15  3:42 UTC|newest]

Thread overview: 51+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-08-05 13:54 [PATCH v4 00/27] Add support for MT8196 clock controllers Laura Nao
2025-08-05 13:54 ` [PATCH v4 01/27] clk: mediatek: clk-pll: Add set/clr regs for shared PLL enable control Laura Nao
2025-08-15  3:03   ` Chen-Yu Tsai
2025-08-05 13:54 ` [PATCH v4 02/27] clk: mediatek: clk-pll: Add ops for PLLs using set/clr regs and FENC Laura Nao
2025-08-15  3:18   ` Chen-Yu Tsai
2025-08-25 12:39     ` Laura Nao
2025-08-28  9:09       ` Laura Nao
2025-08-05 13:54 ` [PATCH v4 03/27] clk: mediatek: clk-mux: Add ops for mux gates with set/clr/upd " Laura Nao
2025-08-15  3:23   ` Chen-Yu Tsai
2025-08-25 12:42     ` Laura Nao
2025-08-05 13:54 ` [PATCH v4 04/27] clk: mediatek: clk-mtk: Introduce mtk_clk_get_hwv_regmap() Laura Nao
2025-08-15  3:25   ` Chen-Yu Tsai
2025-08-05 13:54 ` [PATCH v4 05/27] clk: mediatek: clk-mux: Add ops for mux gates with HW voter and FENC Laura Nao
2025-08-15  3:31   ` Chen-Yu Tsai
2025-08-25 12:45     ` Laura Nao
2025-08-05 13:54 ` [PATCH v4 06/27] clk: mediatek: clk-gate: Refactor mtk_clk_register_gate to use mtk_gate struct Laura Nao
2025-08-15  3:42   ` Chen-Yu Tsai [this message]
2025-08-25 12:49     ` Laura Nao
2025-08-05 13:54 ` [PATCH v4 07/27] clk: mediatek: clk-gate: Add ops for gates with HW voter Laura Nao
2025-08-15  3:37   ` Chen-Yu Tsai
2025-08-25 12:51     ` Laura Nao
2025-08-25 14:50       ` Chen-Yu Tsai
2025-08-26  8:36         ` Laura Nao
2025-08-05 13:54 ` [PATCH v4 08/27] clk: mediatek: clk-mtk: Add MUX_DIV_GATE macro Laura Nao
2025-08-15  3:43   ` Chen-Yu Tsai
2025-08-05 13:54 ` [PATCH v4 09/27] dt-bindings: clock: mediatek: Describe MT8196 clock controllers Laura Nao
2025-08-07  6:58   ` Krzysztof Kozlowski
2025-08-05 13:54 ` [PATCH v4 10/27] clk: mediatek: Add MT8196 apmixedsys clock support Laura Nao
2025-08-05 13:54 ` [PATCH v4 11/27] clk: mediatek: Add MT8196 topckgen " Laura Nao
2025-08-05 13:54 ` [PATCH v4 12/27] clk: mediatek: Add MT8196 topckgen2 " Laura Nao
2025-08-05 13:54 ` [PATCH v4 13/27] clk: mediatek: Add MT8196 vlpckgen " Laura Nao
2025-08-25 13:12   ` Laura Nao
2025-08-05 13:54 ` [PATCH v4 14/27] clk: mediatek: Add MT8196 peripheral " Laura Nao
2025-08-05 13:54 ` [PATCH v4 15/27] clk: mediatek: Add MT8196 ufssys " Laura Nao
2025-08-15  3:50   ` Chen-Yu Tsai
2025-08-25 12:54     ` Laura Nao
2025-08-05 13:54 ` [PATCH v4 16/27] clk: mediatek: Add MT8196 pextpsys " Laura Nao
2025-08-15  3:53   ` Chen-Yu Tsai
2025-08-05 13:54 ` [PATCH v4 17/27] clk: mediatek: Add MT8196 I2C " Laura Nao
2025-08-15  6:13   ` Chen-Yu Tsai
2025-08-05 13:54 ` [PATCH v4 18/27] clk: mediatek: Add MT8196 mcu " Laura Nao
2025-08-05 13:54 ` [PATCH v4 19/27] clk: mediatek: Add MT8196 mdpsys " Laura Nao
2025-08-15  7:16   ` Chen-Yu Tsai
2025-08-05 13:54 ` [PATCH v4 20/27] clk: mediatek: Add MT8196 mfg " Laura Nao
2025-08-05 13:54 ` [PATCH v4 21/27] clk: mediatek: Add MT8196 disp0 " Laura Nao
2025-08-05 13:54 ` [PATCH v4 22/27] clk: mediatek: Add MT8196 disp1 " Laura Nao
2025-08-05 13:54 ` [PATCH v4 23/27] clk: mediatek: Add MT8196 disp-ao " Laura Nao
2025-08-05 13:54 ` [PATCH v4 24/27] clk: mediatek: Add MT8196 ovl0 " Laura Nao
2025-08-05 13:54 ` [PATCH v4 25/27] clk: mediatek: Add MT8196 ovl1 " Laura Nao
2025-08-05 13:54 ` [PATCH v4 26/27] clk: mediatek: Add MT8196 vdecsys " Laura Nao
2025-08-05 13:54 ` [PATCH v4 27/27] clk: mediatek: Add MT8196 vencsys " Laura Nao

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