[PATCH v3 0/4] riscv: dts: starfive: jh7110-common: Sync downstream U-Boot changes

[PATCH v3 0/4] riscv: dts: starfive: jh7110-common: Sync downstream U-Boot changes

[E Shattow]

U-Boot boot loader has adopted using the Linux dt-rebasing tree for dts
with StarFive VisionFive2 board target (and related JH7110 common boards).
Sync the minimum changes from jh7110-common.dtsi needed for boot so these
can be dropped from U-Boot.

Changes since v2:

- 1/5 -> 1/4: Do not replace assigned CPU core or PLL0 clock when adding new
  assignments. Adjust patch name and commit message accordingly.
- 2/5 -> 2/4: Detail reason for qspi setting changes in commit message
- 3/5 -> Drop uart0 clock-frequency patch
- 4/5 -> 3/4: Add reviewed by tag (no change)
- 5/5 -> 4/4: Follow dts coding style sort order. Add bootph-pre-ram hint
  for mmc interfaces

Note: mmc boot source modes of JH7110 loader on mask ROM are deprecated as
of StarFive JH7110 User Guide 1.2 revision. The loader expects data within
range of LBA 0 and LBA 1 in conflict with GUID Partition Table.

SD Card and eMMC boot media are prepared as follows:

# GPT partition SD Card or eMMC as
# 1: Secondary Program Loader @ 0x200000
# 2: Main payload area for use by SPL
# 3: EFI System Partition
sgdisk --clear \
  --new=1:2M:+2M --typecode=1:2E54B353-1271-4842-806F-E436D6AF6985 \
  --new=2:4M:+4M --typecode=2:5B193300-FC78-40CD-8002-E86C45580B47 \
  --new=3:8M:+100M --typecode=3:EF00 /dev/sdX

# Write offset value in bytes of loader 'backup section' SPL as part1 @ 2M
python3 <<-EOF
with open("/dev/sdX", "r+b") as f:
  f.seek(0x0004)
  f.write((0x200000).to_bytes(4, "little"))
EOF

# Write invalid CRC to trigger 'Main section boot fail,use backup section'
python3 <<-EOF
with open("/dev/sdX", "r+b") as f:
  f.seek(0x0290)
  f.write((0x5A5A5A5A).to_bytes(4, "little"))
EOF

E Shattow (4):
  riscv: dts: starfive: jh7110-common: add CPU BUS PERH QSPI clocks to
    syscrg
  riscv: dts: starfive: jh7110-common: qspi flash setting read-delay 2
    cycles max 100MHz
  riscv: dts: starfive: jh7110-common: add eeprom node to i2c5
  riscv: dts: starfive: jh7110-common: bootph-pre-ram hinting needed by
    boot loader

 .../boot/dts/starfive/jh7110-common.dtsi      | 31 ++++++++++++++++---
 1 file changed, 27 insertions(+), 4 deletions(-)


base-commit: ebd297a2affadb6f6f4d2e5d975c1eda18ac762d
-- 
2.49.0

[PATCH v3 1/4] riscv: dts: starfive: jh7110-common: add CPU BUS PERH QSPI clocks to syscrg

[E Shattow]

Add syscrg clock assignments for CPU, BUS, PERH, and QSPI as required by
boot loader before kernel.

Signed-off-by: E Shattow <e@freeshell.de>
---
 arch/riscv/boot/dts/starfive/jh7110-common.dtsi | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
index c2f70f5e2918..f1489e9bb83e 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
@@ -353,9 +353,17 @@ &spi0 {
 };
 
 &syscrg {
-	assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>,
+	assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_ROOT>,
+			  <&syscrg JH7110_SYSCLK_BUS_ROOT>,
+			  <&syscrg JH7110_SYSCLK_PERH_ROOT>,
+			  <&syscrg JH7110_SYSCLK_QSPI_REF>,
+			  <&syscrg JH7110_SYSCLK_CPU_CORE>,
 			  <&pllclk JH7110_PLLCLK_PLL0_OUT>;
-	assigned-clock-rates = <500000000>, <1500000000>;
+	assigned-clock-parents = <&pllclk JH7110_PLLCLK_PLL0_OUT>,
+				 <&pllclk JH7110_PLLCLK_PLL2_OUT>,
+				 <&pllclk JH7110_PLLCLK_PLL2_OUT>,
+				 <&syscrg JH7110_SYSCLK_QSPI_REF_SRC>;
+	assigned-clock-rates = <0>, <0>, <0>, <0>, <500000000>, <1500000000>;
 };
 
 &sysgpio {
-- 
2.49.0

[PATCH v3 2/4] riscv: dts: starfive: jh7110-common: qspi flash setting read-delay 2 cycles max 100MHz

[E Shattow]

Use qspi flash read-delay and spi-max-frequency settings compatible with
U-Boot bootloader.

Observations from testing on Pine64 Star64 hardware within U-Boot bootloader
and read-delay=2 are spi-max-frequency less than 49.8MHz fails to write,
corrupt data writes at 25MHz to 49.799999MHz, and valid data writes at
49.8MHz to 100MHz (not tested above 100MHz). No valid spi-max-frequency
was found for 1<read-delay<=3 and corrupt data with read-delay=3.

Looking around the Linux codebase it is common to see read-delay 2 cycles
with spi-max-frequency 100MHz and testing confirms this to work in both
U-Boot and Linux.

Signed-off-by: E Shattow <e@freeshell.de>
Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
---
 arch/riscv/boot/dts/starfive/jh7110-common.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
index f1489e9bb83e..5c525686c043 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
@@ -317,8 +317,8 @@ &qspi {
 	nor_flash: flash@0 {
 		compatible = "jedec,spi-nor";
 		reg = <0>;
-		cdns,read-delay = <5>;
-		spi-max-frequency = <12000000>;
+		cdns,read-delay = <2>;
+		spi-max-frequency = <100000000>;
 		cdns,tshsl-ns = <1>;
 		cdns,tsd2d-ns = <1>;
 		cdns,tchsh-ns = <1>;
-- 
2.49.0

[PATCH v3 3/4] riscv: dts: starfive: jh7110-common: add eeprom node to i2c5

[E Shattow]

StarFive VisionFive2 and similar JH7110 boards have an eeprom compatible
with Atmel 24c04. Add the node so this may be used with the at24 driver.

Signed-off-by: E Shattow <e@freeshell.de>
Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
---
 arch/riscv/boot/dts/starfive/jh7110-common.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
index 5c525686c043..f1dc45b98e1d 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
@@ -245,6 +245,12 @@ emmc_vdd: aldo4 {
 			};
 		};
 	};
+
+	eeprom@50 {
+		compatible = "atmel,24c04";
+		reg = <0x50>;
+		pagesize = <16>;
+	};
 };
 
 &i2c6 {
-- 
2.49.0

[PATCH v3 4/4] riscv: dts: starfive: jh7110-common: bootph-pre-ram hinting needed by boot loader

[E Shattow]

Add bootph-pre-ram hinting to jh7110-common.dtsi:
  - i2c5_pins and i2c-pins subnode for connection to eeprom
  - eeprom node
  - qspi flash configuration subnode
  - memory node
  - mmc0 for eMMC
  - mmc1 for SD Card
  - uart0 for serial console

  With this the U-Boot SPL secondary program loader may drop such overrides.

Signed-off-by: E Shattow <e@freeshell.de>
---
 arch/riscv/boot/dts/starfive/jh7110-common.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
index f1dc45b98e1d..d2cdb2f276c3 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
@@ -28,6 +28,7 @@ chosen {
 	memory@40000000 {
 		device_type = "memory";
 		reg = <0x0 0x40000000 0x1 0x0>;
+		bootph-pre-ram;
 	};
 
 	gpio-restart {
@@ -249,6 +250,7 @@ emmc_vdd: aldo4 {
 	eeprom@50 {
 		compatible = "atmel,24c04";
 		reg = <0x50>;
+		bootph-pre-ram;
 		pagesize = <16>;
 	};
 };
@@ -268,6 +270,7 @@ &mmc0 {
 	assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>;
 	assigned-clock-rates = <50000000>;
 	bus-width = <8>;
+	bootph-pre-ram;
 	cap-mmc-highspeed;
 	mmc-ddr-1_8v;
 	mmc-hs200-1_8v;
@@ -285,6 +288,7 @@ &mmc1 {
 	assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>;
 	assigned-clock-rates = <50000000>;
 	bus-width = <4>;
+	bootph-pre-ram;
 	no-sdio;
 	no-mmc;
 	cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
@@ -323,6 +327,7 @@ &qspi {
 	nor_flash: flash@0 {
 		compatible = "jedec,spi-nor";
 		reg = <0>;
+		bootph-pre-ram;
 		cdns,read-delay = <2>;
 		spi-max-frequency = <100000000>;
 		cdns,tshsl-ns = <1>;
@@ -402,6 +407,8 @@ GPOEN_SYS_I2C2_DATA,
 	};
 
 	i2c5_pins: i2c5-0 {
+		bootph-pre-ram;
+
 		i2c-pins {
 			pinmux = <GPIOMUX(19, GPOUT_LOW,
 					      GPOEN_SYS_I2C5_CLK,
@@ -410,6 +417,7 @@ GPI_SYS_I2C5_CLK)>,
 					      GPOEN_SYS_I2C5_DATA,
 					      GPI_SYS_I2C5_DATA)>;
 			bias-disable; /* external pull-up */
+			bootph-pre-ram;
 			input-enable;
 			input-schmitt-enable;
 		};
@@ -638,6 +646,7 @@ GPOEN_DISABLE,
 };
 
 &uart0 {
+	bootph-pre-ram;
 	pinctrl-names = "default";
 	pinctrl-0 = <&uart0_pins>;
 	status = "okay";
-- 
2.49.0

Re: [PATCH v3 1/4] riscv: dts: starfive: jh7110-common: add CPU BUS PERH QSPI clocks to syscrg

[Emil Renner Berthing]

E Shattow wrote:
> Add syscrg clock assignments for CPU, BUS, PERH, and QSPI as required by
> boot loader before kernel.
>
> Signed-off-by: E Shattow <e@freeshell.de>

Thanks!

Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>

> ---
>  arch/riscv/boot/dts/starfive/jh7110-common.dtsi | 12 ++++++++++--
>  1 file changed, 10 insertions(+), 2 deletions(-)
>
> diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
> index c2f70f5e2918..f1489e9bb83e 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
> @@ -353,9 +353,17 @@ &spi0 {
>  };
>
>  &syscrg {
> -	assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>,
> +	assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_ROOT>,
> +			  <&syscrg JH7110_SYSCLK_BUS_ROOT>,
> +			  <&syscrg JH7110_SYSCLK_PERH_ROOT>,
> +			  <&syscrg JH7110_SYSCLK_QSPI_REF>,
> +			  <&syscrg JH7110_SYSCLK_CPU_CORE>,
>  			  <&pllclk JH7110_PLLCLK_PLL0_OUT>;
> -	assigned-clock-rates = <500000000>, <1500000000>;
> +	assigned-clock-parents = <&pllclk JH7110_PLLCLK_PLL0_OUT>,
> +				 <&pllclk JH7110_PLLCLK_PLL2_OUT>,
> +				 <&pllclk JH7110_PLLCLK_PLL2_OUT>,
> +				 <&syscrg JH7110_SYSCLK_QSPI_REF_SRC>;
> +	assigned-clock-rates = <0>, <0>, <0>, <0>, <500000000>, <1500000000>;
>  };
>
>  &sysgpio {
> --
> 2.49.0
>

Re: [PATCH v3 2/4] riscv: dts: starfive: jh7110-common: qspi flash setting read-delay 2 cycles max 100MHz

[Emil Renner Berthing]

E Shattow wrote:
> Use qspi flash read-delay and spi-max-frequency settings compatible with
> U-Boot bootloader.
>
> Observations from testing on Pine64 Star64 hardware within U-Boot bootloader
> and read-delay=2 are spi-max-frequency less than 49.8MHz fails to write,
> corrupt data writes at 25MHz to 49.799999MHz, and valid data writes at
> 49.8MHz to 100MHz (not tested above 100MHz). No valid spi-max-frequency
> was found for 1<read-delay<=3 and corrupt data with read-delay=3.
>
> Looking around the Linux codebase it is common to see read-delay 2 cycles
> with spi-max-frequency 100MHz and testing confirms this to work in both
> U-Boot and Linux.
>
> Signed-off-by: E Shattow <e@freeshell.de>
> Reviewed-by: Hal Feng <hal.feng@starfivetech.com>

Thanks!

Acked-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>

> ---
>  arch/riscv/boot/dts/starfive/jh7110-common.dtsi | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
> index f1489e9bb83e..5c525686c043 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
> @@ -317,8 +317,8 @@ &qspi {
>  	nor_flash: flash@0 {
>  		compatible = "jedec,spi-nor";
>  		reg = <0>;
> -		cdns,read-delay = <5>;
> -		spi-max-frequency = <12000000>;
> +		cdns,read-delay = <2>;
> +		spi-max-frequency = <100000000>;
>  		cdns,tshsl-ns = <1>;
>  		cdns,tsd2d-ns = <1>;
>  		cdns,tchsh-ns = <1>;
> --
> 2.49.0
>

Re: [PATCH v3 4/4] riscv: dts: starfive: jh7110-common: bootph-pre-ram hinting needed by boot loader

[Emil Renner Berthing]

E Shattow wrote:
> Add bootph-pre-ram hinting to jh7110-common.dtsi:
>   - i2c5_pins and i2c-pins subnode for connection to eeprom
>   - eeprom node
>   - qspi flash configuration subnode
>   - memory node
>   - mmc0 for eMMC
>   - mmc1 for SD Card
>   - uart0 for serial console
>
>   With this the U-Boot SPL secondary program loader may drop such overrides.
>
> Signed-off-by: E Shattow <e@freeshell.de>

Acked-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>

> ---
>  arch/riscv/boot/dts/starfive/jh7110-common.dtsi | 9 +++++++++
>  1 file changed, 9 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
> index f1dc45b98e1d..d2cdb2f276c3 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
> @@ -28,6 +28,7 @@ chosen {
>  	memory@40000000 {
>  		device_type = "memory";
>  		reg = <0x0 0x40000000 0x1 0x0>;
> +		bootph-pre-ram;
>  	};
>
>  	gpio-restart {
> @@ -249,6 +250,7 @@ emmc_vdd: aldo4 {
>  	eeprom@50 {
>  		compatible = "atmel,24c04";
>  		reg = <0x50>;
> +		bootph-pre-ram;
>  		pagesize = <16>;
>  	};
>  };
> @@ -268,6 +270,7 @@ &mmc0 {
>  	assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>;
>  	assigned-clock-rates = <50000000>;
>  	bus-width = <8>;
> +	bootph-pre-ram;
>  	cap-mmc-highspeed;
>  	mmc-ddr-1_8v;
>  	mmc-hs200-1_8v;
> @@ -285,6 +288,7 @@ &mmc1 {
>  	assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>;
>  	assigned-clock-rates = <50000000>;
>  	bus-width = <4>;
> +	bootph-pre-ram;
>  	no-sdio;
>  	no-mmc;
>  	cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
> @@ -323,6 +327,7 @@ &qspi {
>  	nor_flash: flash@0 {
>  		compatible = "jedec,spi-nor";
>  		reg = <0>;
> +		bootph-pre-ram;
>  		cdns,read-delay = <2>;
>  		spi-max-frequency = <100000000>;
>  		cdns,tshsl-ns = <1>;
> @@ -402,6 +407,8 @@ GPOEN_SYS_I2C2_DATA,
>  	};
>
>  	i2c5_pins: i2c5-0 {
> +		bootph-pre-ram;
> +
>  		i2c-pins {
>  			pinmux = <GPIOMUX(19, GPOUT_LOW,
>  					      GPOEN_SYS_I2C5_CLK,
> @@ -410,6 +417,7 @@ GPI_SYS_I2C5_CLK)>,
>  					      GPOEN_SYS_I2C5_DATA,
>  					      GPI_SYS_I2C5_DATA)>;
>  			bias-disable; /* external pull-up */
> +			bootph-pre-ram;
>  			input-enable;
>  			input-schmitt-enable;
>  		};
> @@ -638,6 +646,7 @@ GPOEN_DISABLE,
>  };
>
>  &uart0 {
> +	bootph-pre-ram;
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&uart0_pins>;
>  	status = "okay";
> --
> 2.49.0
>

Re: [PATCH v3 0/4] riscv: dts: starfive: jh7110-common: Sync downstream U-Boot changes

[Emil Renner Berthing]

E Shattow wrote:
> U-Boot boot loader has adopted using the Linux dt-rebasing tree for dts
> with StarFive VisionFive2 board target (and related JH7110 common boards).
> Sync the minimum changes from jh7110-common.dtsi needed for boot so these
> can be dropped from U-Boot.
>
> Changes since v2:
>
> - 1/5 -> 1/4: Do not replace assigned CPU core or PLL0 clock when adding new
>   assignments. Adjust patch name and commit message accordingly.
> - 2/5 -> 2/4: Detail reason for qspi setting changes in commit message
> - 3/5 -> Drop uart0 clock-frequency patch
> - 4/5 -> 3/4: Add reviewed by tag (no change)
> - 5/5 -> 4/4: Follow dts coding style sort order. Add bootph-pre-ram hint
>   for mmc interfaces
>
> Note: mmc boot source modes of JH7110 loader on mask ROM are deprecated as
> of StarFive JH7110 User Guide 1.2 revision. The loader expects data within
> range of LBA 0 and LBA 1 in conflict with GUID Partition Table.
>
> SD Card and eMMC boot media are prepared as follows:
>
> # GPT partition SD Card or eMMC as
> # 1: Secondary Program Loader @ 0x200000
> # 2: Main payload area for use by SPL
> # 3: EFI System Partition
> sgdisk --clear \
>   --new=1:2M:+2M --typecode=1:2E54B353-1271-4842-806F-E436D6AF6985 \
>   --new=2:4M:+4M --typecode=2:5B193300-FC78-40CD-8002-E86C45580B47 \
>   --new=3:8M:+100M --typecode=3:EF00 /dev/sdX
>
> # Write offset value in bytes of loader 'backup section' SPL as part1 @ 2M
> python3 <<-EOF
> with open("/dev/sdX", "r+b") as f:
>   f.seek(0x0004)
>   f.write((0x200000).to_bytes(4, "little"))
> EOF
>
> # Write invalid CRC to trigger 'Main section boot fail,use backup section'
> python3 <<-EOF
> with open("/dev/sdX", "r+b") as f:
>   f.seek(0x0290)
>   f.write((0x5A5A5A5A).to_bytes(4, "little"))
> EOF

This series looks good to me now. Thank you.

/Emil

>
> E Shattow (4):
>   riscv: dts: starfive: jh7110-common: add CPU BUS PERH QSPI clocks to
>     syscrg
>   riscv: dts: starfive: jh7110-common: qspi flash setting read-delay 2
>     cycles max 100MHz
>   riscv: dts: starfive: jh7110-common: add eeprom node to i2c5
>   riscv: dts: starfive: jh7110-common: bootph-pre-ram hinting needed by
>     boot loader
>
>  .../boot/dts/starfive/jh7110-common.dtsi      | 31 ++++++++++++++++---
>  1 file changed, 27 insertions(+), 4 deletions(-)
>
>
> base-commit: ebd297a2affadb6f6f4d2e5d975c1eda18ac762d
> --
> 2.49.0
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv

Re: [PATCH v3 0/4] riscv: dts: starfive: jh7110-common: Sync downstream U-Boot changes

[Conor Dooley]

From: Conor Dooley <conor.dooley@microchip.com>

On Fri, 02 May 2025 03:30:40 -0700, E Shattow wrote:
> U-Boot boot loader has adopted using the Linux dt-rebasing tree for dts
> with StarFive VisionFive2 board target (and related JH7110 common boards).
> Sync the minimum changes from jh7110-common.dtsi needed for boot so these
> can be dropped from U-Boot.
> 
> Changes since v2:
> 
> [...]

Applied to riscv-dt-for-next, thanks!

[1/4] riscv: dts: starfive: jh7110-common: add CPU BUS PERH QSPI clocks to syscrg
      https://git.kernel.org/conor/c/724a6718ce21
[2/4] riscv: dts: starfive: jh7110-common: qspi flash setting read-delay 2 cycles max 100MHz
      https://git.kernel.org/conor/c/59404dceb303
[3/4] riscv: dts: starfive: jh7110-common: add eeprom node to i2c5
      https://git.kernel.org/conor/c/635918111453
[4/4] riscv: dts: starfive: jh7110-common: bootph-pre-ram hinting needed by boot loader
      https://git.kernel.org/conor/c/d50108706a63

Thanks,
Conor.