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AJvYcCWwGpD+qxDYicrHKHce+ydwqoGpJUdn9iddnP30rrOU2ic+m+VHuPh75hfaJZJol5/3GIUky9Pzol4ihEw=@vger.kernel.org X-Gm-Message-State: AOJu0YxNzOMnE6T7oGl8gNUCPyfZE9Jcab12VmtK+o+2cEcZGo0XQdTJ TMYHmdmSt5uLGmsRtMotfAE655IQP1a2IrR6JOqm/1nwWkUz8/iKrmjA1RXeIUwCNhKBeRx+KAA xrLixb/pJRe1ox+RMP6stKiwvIo+IvJjwZOApink2tQ== X-Gm-Gg: ASbGnculY/Vl3nb5hFDagPcnFUa2TeIKZ/V/PwrCBtfaKNYi5xvUFE8oGebtrmhjPk7 ExO8K7ZqssVKO2X0IY5oZxVg6Fjv9Wjkjh8QsQNIc1ktBOVDFNpEMsd67btM91NR/sjsbXo6e2Q Andvw7m19mnQGQ4C1vSkWeWdvDpKeRB8oX+dpO87BrBaZv50R2HVObDVElGUkaMvMnmrqL0OShc L4chbMsSt5gsGBs1MCu0ABmWur51x/PwYcVtcI= X-Google-Smtp-Source: AGHT+IGjT2OYHV9mzILkObbuSFLpi9Xf+oP+6Uws6rzp7smTv5kAfs8i0u8RIWSnII9gINWFQq3zddWVjDxSq4eH8MM= X-Received: by 2002:a05:6512:245b:b0:55f:51b3:9419 with SMTP id 2adb3069b0e04-55f51b39621mr1791521e87.50.1756388214118; Thu, 28 Aug 2025 06:36:54 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20250815-pinctrl-gpio-pinfuncs-v5-0-955de9fd91db@linaro.org> <534ad082-08fa-42c0-9c24-f0c11af7d5b2@sirena.org.uk> <1804d9dc-8814-47d4-af88-c819c3f17bc0@sirena.org.uk> In-Reply-To: From: Bartosz Golaszewski Date: Thu, 28 Aug 2025 15:36:43 +0200 X-Gm-Features: Ac12FXwlaqUs0TeuR0_lKNQwkWNyJ4q4Po7liyAa4ioyozolnG0jRU9pqqtYG0I Message-ID: Subject: Re: [PATCH v5 00/15] pinctrl: introduce the concept of a GPIO pin function category To: Mark Brown Cc: Linus Walleij , Andy Shevchenko , Bjorn Andersson , Konrad Dybcio , Alexey Klimov , Lorenzo Bianconi , Sean Wang , Matthias Brugger , AngeloGioacchino Del Regno , Paul Cercueil , Kees Cook , Andy Shevchenko , Andrew Morton , David Hildenbrand , Lorenzo Stoakes , "Liam R. Howlett" , Vlastimil Babka , Mike Rapoport , Suren Baghdasaryan , Michal Hocko , Dong Aisheng , Fabio Estevam , Shawn Guo , Jacky Bai , Pengutronix Kernel Team , NXP S32 Linux Team , Sascha Hauer , Tony Lindgren , Haojian Zhuang , Geert Uytterhoeven , Greg Kroah-Hartman , "Rafael J. Wysocki" , Danilo Krummrich , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mm@kvack.org, imx@lists.linux.dev, linux-omap@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Bartosz Golaszewski , Chen-Yu Tsai , Konrad Dybcio Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Thu, Aug 28, 2025 at 10:51=E2=80=AFAM Mark Brown wr= ote: > > On Wed, Aug 27, 2025 at 06:46:28PM +0200, Bartosz Golaszewski wrote: > > On Wed, Aug 27, 2025 at 12:22=E2=80=AFPM Mark Brown wrote: > > > > I've just got the log I linked above. > > > So, I've been looking at this bisect email and clicking the links to > > LAVA jobs and I can't find anything. Does it fail to build? Fail at > > run-time? I'm not sure how to read this. > > It's failing prior to putting any output on the console. I was also > seeing an issue on i.MX6 so it might be all i.MX boards, same issue: > > https://lava.sirena.org.uk/scheduler/job/1697667 > > so it's possibly all the i.MX platforms failing. Not even with earlycon? That's weird. There are no smatch warnings on this patch and I can't see anything obviously wrong upon visual inspection. I fixed all other issues but this one I can't test. :( Bartosz