Re: [PATCH v3 6/7] pinctrl: renesas: rzg2l: Add PFC_OEN support for RZ/G3E SoC

[Geert Uytterhoeven <geert@linux-m68k.org>]

On Wed, 6 Aug 2025 at 21:56, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Add support for configuring the PFC_OEN register on the RZ/G3E SoC to
> enable output-enable control for specific pins. On this SoC, certain
> pins such as TXC_TXCLK need to support switching between input and
> output modes depending on the PHY interface mode (e.g., MII vs RGMII).
> This functionality maps to the 'output-enable' property in the device
> tree and requires explicit control via the PFC_OEN register.
>
> This change updates the r9a09g047_variable_pin_cfg array to mark PB1, PE1,
> PL0, PL1, PL2, and PL4 with the PIN_CFG_OEN flag to indicate output-enable
> support. A new helper, rzg3e_pin_to_oen_bit(), is introduced to map these
> pin names to their respective OEN bit positions, and the corresponding
> callbacks are wired into the RZ/G3E SoC configuration using the generic
> rzg2l_read_oen() and rzg2l_write_oen() accessors. Additionally, the GPIO
> configuration for the PB, PE, and PL ports is updated to use the variable
> port pack macro, enabling per-pin configuration necessary for OEN handling.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> v2->v3:
> - Added Reviewed-by tag from Geert.

Thanks, will queue in renesas-pinctrl for v6.18.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

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when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds