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[209.85.217.53]) by smtp.gmail.com with ESMTPSA id 71dfb90a1353d-539b0289540sm257408e0c.18.2025.08.07.00.02.51 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 07 Aug 2025 00:02:52 -0700 (PDT) Received: by mail-vs1-f53.google.com with SMTP id ada2fe7eead31-4fbfbda957fso236450137.2; Thu, 07 Aug 2025 00:02:51 -0700 (PDT) X-Forwarded-Encrypted: i=1; AJvYcCUXDzBsS0kFQ8TNG0G7Vm+a9BH39IcXyX3g79Y5S0G3WtzG9Ec0SgZn6foMBijO/JvBax9zqzlku6OuCzLIKKe9MYQ=@vger.kernel.org, AJvYcCWRwr+yV0Q9QVNfRmHqU/IukQznpGv7Q5CMk/4PxHqh6FZfESGODFV80h8Pi21lN+yJHRLmBqMesEVndkst@vger.kernel.org, AJvYcCX1HyeGAk4VsN5xox63QehWwZPzABl3wLGjnOwGIikgnbEwMdAHCf2xBGUC6rD0LoGh2367KXFjwJnU@vger.kernel.org X-Received: by 2002:a05:6102:510e:b0:4e2:ecd8:a27 with SMTP id ada2fe7eead31-503722a411emr2554414137.4.1754550171636; Thu, 07 Aug 2025 00:02:51 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20250806195555.1372317-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20250806195555.1372317-7-prabhakar.mahadev-lad.rj@bp.renesas.com> In-Reply-To: <20250806195555.1372317-7-prabhakar.mahadev-lad.rj@bp.renesas.com> From: Geert Uytterhoeven Date: Thu, 7 Aug 2025 09:02:40 +0200 X-Gmail-Original-Message-ID: X-Gm-Features: Ac12FXynKZpQCNwGow0EhYowF_NXVOdWV_LRqcM-AyswTMbCtS1DyvFrvMVaDwU Message-ID: Subject: Re: [PATCH v3 6/7] pinctrl: renesas: rzg2l: Add PFC_OEN support for RZ/G3E SoC To: Prabhakar Cc: Linus Walleij , linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Biju Das , Fabrizio Castro , Lad Prabhakar Content-Type: text/plain; charset="UTF-8" On Wed, 6 Aug 2025 at 21:56, Prabhakar wrote: > From: Lad Prabhakar > > Add support for configuring the PFC_OEN register on the RZ/G3E SoC to > enable output-enable control for specific pins. On this SoC, certain > pins such as TXC_TXCLK need to support switching between input and > output modes depending on the PHY interface mode (e.g., MII vs RGMII). > This functionality maps to the 'output-enable' property in the device > tree and requires explicit control via the PFC_OEN register. > > This change updates the r9a09g047_variable_pin_cfg array to mark PB1, PE1, > PL0, PL1, PL2, and PL4 with the PIN_CFG_OEN flag to indicate output-enable > support. A new helper, rzg3e_pin_to_oen_bit(), is introduced to map these > pin names to their respective OEN bit positions, and the corresponding > callbacks are wired into the RZ/G3E SoC configuration using the generic > rzg2l_read_oen() and rzg2l_write_oen() accessors. Additionally, the GPIO > configuration for the PB, PE, and PL ports is updated to use the variable > port pack macro, enabling per-pin configuration necessary for OEN handling. > > Signed-off-by: Lad Prabhakar > Reviewed-by: Geert Uytterhoeven > --- > v2->v3: > - Added Reviewed-by tag from Geert. Thanks, will queue in renesas-pinctrl for v6.18. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds