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From: Geert Uytterhoeven <geert@linux-m68k.org>
To: Claudiu Beznea <claudiu.beznea@tuxon.dev>
Cc: Krzysztof Kozlowski <krzk@kernel.org>,
	Bjorn Helgaas <helgaas@kernel.org>,
	bhelgaas@google.com,  lpieralisi@kernel.org,
	kwilczynski@kernel.org, mani@kernel.org,  robh@kernel.org,
	krzk+dt@kernel.org, conor+dt@kernel.org,
	 geert+renesas@glider.be, magnus.damm@gmail.com,
	catalin.marinas@arm.com,  will@kernel.org,
	mturquette@baylibre.com, sboyd@kernel.org,
	 p.zabel@pengutronix.de, lizhi.hou@amd.com,
	linux-pci@vger.kernel.org,  linux-renesas-soc@vger.kernel.org,
	devicetree@vger.kernel.org,  linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,  linux-clk@vger.kernel.org,
	Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>,
	 Wolfram Sang <wsa+renesas@sang-engineering.com>
Subject: Re: [PATCH v3 4/9] dt-bindings: PCI: renesas,r9a08g045s33-pcie: Add documentation for the PCIe IP on Renesas RZ/G3S
Date: Fri, 8 Aug 2025 14:03:53 +0200	[thread overview]
Message-ID: <CAMuHMdVS7VRBj3Neh7P1FDfaG7uPfpny4tFsDTk6tsmiYu3S+g@mail.gmail.com> (raw)
In-Reply-To: <0addc570-a3c6-4d7e-9cbd-06eedd2447bb@tuxon.dev>

Hi Claudiu,

On Fri, 8 Aug 2025 at 13:44, Claudiu Beznea <claudiu.beznea@tuxon.dev> wrote:
> On 09.07.2025 16:43, Krzysztof Kozlowski wrote:
> > On 09/07/2025 15:24, Bjorn Helgaas wrote:
> >> On Wed, Jul 09, 2025 at 08:47:05AM +0200, Krzysztof Kozlowski wrote:
> >>> On 08/07/2025 18:34, Bjorn Helgaas wrote:
> >>>> On Fri, Jul 04, 2025 at 07:14:04PM +0300, Claudiu wrote:
> >>>>> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> >>>>>
> >>>>> The PCIe IP available on the Renesas RZ/G3S complies with the PCI Express
> >>>>> Base Specification 4.0. It is designed for root complex applications and
> >>>>> features a single-lane (x1) implementation. Add documentation for it.
> >>>>
> >>>>> +++ b/Documentation/devicetree/bindings/pci/renesas,r9a08g045s33-pcie.yaml
> >>>>
> >>>> The "r9a08g045s33" in the filename seems oddly specific.  Does it
> >>>> leave room for descendants of the current chip that will inevitably be
> >>>> added in the future?  Most bindings are named with a fairly generic
> >>>> family name, e.g., "fsl,layerscape", "hisilicon,kirin", "intel,
> >>>> keembay", "samsung,exynos", etc.
> >>>>
> >>>
> >>> Bindings should be named by compatible, not in a generic way, so name is
> >>> correct. It can always grow with new compatibles even if name matches
> >>> old one, it's not a problem.
> >>
> >> Ok, thanks!
> >>
> >> I guess that means I'm casting shade on the "r9a08g045s33" compatible.
> >> I suppose it means something to somebody.
> >
> > Well, I hope it matches the name of the SoC, from which the compatible
> > should come :)
>
> The r9a08g45s33 is the part number of a device from the RZ/G3S group. This
> particular device from RZ/G3S group supports PCIe.
>
> In the RZ/G3S group there are more SoC variants (each with its own part
> number). Not all support PCIe. To differentiate b/w PCIe and non-PCIe
> variants it has been chosen to use the full part number here.
>
> The available RZ/G3S part numbers are listed in Table 1.1 Product Lineup at [1]
>
> (The following steps should be followed to access the manual:
> 1/ Click the "User Manual" button
> 2/ Click "Confirm"; this will start downloading an archive
> 3/ Open the downloaded archive
> 4/ Navigate to r01uh1014ej*-rzg3s-users-manual-hardware -> Deliverables
> 5/ Open the file r01uh1014ej*-rzg3s.pdf)
>
> We use a similar compatible scheme in other drivers.
>
> Geert, I may be wrong. Please correct me otherwise, as I don't have the
> full picture of this.
>
> Maybe, the other variant would be to use "renesas,rzg3s-pcie", or maybe a
> more generic one "renesas,rz-pcie" (though I think this last one is too
> generic).

Both would be too generic for the myriad of RZ devices.

AFAIU, the R9A08G045Sxx variants are really the same SoC, with some
hardware modules disabled/nonfunctional.  This is typically handled by:
  1. Using the base part number (r9a08g045) in the compatible value,
  2. Having the device node in the base .dtsi,
  3. Deleting nodes in the variant-specific .dtsi file when needed
     (see e.g. arch/arm64/boot/dts/renesas/r9a09g047{,e[35]7}.dtsi)

Hence as R9A08G045S13, R9A08G045S17, R9A08G045S33, and
R9A08G045S37 all have PCIe, I think it is more appropriate
to use "renesas,r9a08g045-pcie" as the compatible value than
"renesas,r9a08g045s33-pcie".

> Geert, please let us know if you have some suggestions here with regards to
> the compatible. The IP on RZ/G3S is compatible also with the one in RZ/V2H,
> RZ/G3E.

RZ/V2H and RZ/G3E can use "renesas,r9a09g057-pcie" resp.
"renesas,r9a09g047-pcie", with "renesas,r9a08g045-pcie" as a fallback.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

  reply	other threads:[~2025-08-08 12:04 UTC|newest]

Thread overview: 47+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-07-04 16:14 [PATCH v3 0/9] PCI: rzg3s-host: Add PCIe driver for Renesas RZ/G3S SoC Claudiu
2025-07-04 16:14 ` [PATCH v3 1/9] soc: renesas: rz-sysc: Add syscon/regmap support Claudiu
2025-07-04 16:14 ` [PATCH v3 2/9] clk: renesas: r9a08g045: Add clocks and resets support for PCIe Claudiu
2025-08-04 10:25   ` Geert Uytterhoeven
2025-07-04 16:14 ` [PATCH v3 3/9] PCI: of_property: Restore the arguments of the next level parent Claudiu
2025-08-20 17:47   ` Manivannan Sadhasivam
2025-08-21  7:40     ` Claudiu Beznea
2025-08-30  4:10       ` Manivannan Sadhasivam
2025-07-04 16:14 ` [PATCH v3 4/9] dt-bindings: PCI: renesas,r9a08g045s33-pcie: Add documentation for the PCIe IP on Renesas RZ/G3S Claudiu
2025-07-08 16:34   ` Bjorn Helgaas
2025-07-09  6:47     ` Krzysztof Kozlowski
2025-07-09 13:24       ` Bjorn Helgaas
2025-07-09 13:43         ` Krzysztof Kozlowski
2025-08-08 11:26           ` Claudiu Beznea
2025-08-08 12:03             ` Geert Uytterhoeven [this message]
2025-08-08 11:25     ` Claudiu Beznea
2025-08-08 16:23       ` Bjorn Helgaas
2025-08-28 19:11       ` claudiu beznea
2025-08-28 19:36         ` Bjorn Helgaas
2025-08-29  5:03           ` claudiu beznea
2025-07-04 16:14 ` [PATCH v3 5/9] PCI: rzg3s-host: Add Initial PCIe Host Driver for Renesas RZ/G3S SoC Claudiu
2025-07-08 19:24   ` Bjorn Helgaas
2025-08-08 11:24     ` Claudiu Beznea
2025-08-30  6:59   ` Manivannan Sadhasivam
2025-08-30 11:22     ` Claudiu Beznea
2025-08-31  4:07       ` Manivannan Sadhasivam
2025-09-01  9:25         ` Geert Uytterhoeven
2025-09-01 14:03           ` Manivannan Sadhasivam
2025-09-01 14:22             ` Geert Uytterhoeven
2025-09-01 15:54               ` Manivannan Sadhasivam
2025-07-04 16:14 ` [PATCH v3 6/9] arm64: dts: renesas: r9a08g045s33: Add PCIe node Claudiu
2025-08-08 12:13   ` Geert Uytterhoeven
2025-07-04 16:14 ` [PATCH v3 7/9] arm64: dts: renesas: rzg3s-smarc-som: Update dma-ranges for PCIe Claudiu
2025-07-07  8:18   ` Biju Das
2025-07-08 10:09     ` Claudiu Beznea
2025-07-09  5:05       ` Biju Das
2025-08-08 11:28         ` Claudiu Beznea
2025-08-08 11:44           ` Biju Das
2025-08-08 12:03             ` Claudiu Beznea
2025-08-08 11:45         ` Geert Uytterhoeven
2025-07-08 16:55   ` Bjorn Helgaas
2025-08-08 11:24     ` Claudiu Beznea
2025-07-04 16:14 ` [PATCH v3 8/9] arm64: dts: renesas: rzg3s-smarc: Enable PCIe Claudiu
2025-07-04 16:14 ` [PATCH v3 9/9] arm64: defconfig: Enable PCIe for the Renesas RZ/G3S SoC Claudiu
2025-07-07  6:41 ` [PATCH v3 0/9] PCI: rzg3s-host: Add PCIe driver for " Wolfram Sang
2025-07-07  8:05   ` Claudiu Beznea
2025-07-07 12:01     ` Wolfram Sang

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