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[209.85.217.41]) by smtp.gmail.com with ESMTPSA id a1e0cc1a2514c-87f23915d10sm1747943241.7.2025.06.19.08.23.49 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 19 Jun 2025 08:23:49 -0700 (PDT) Received: by mail-vs1-f41.google.com with SMTP id ada2fe7eead31-4e8110ac0f5so242258137.0; Thu, 19 Jun 2025 08:23:49 -0700 (PDT) X-Forwarded-Encrypted: i=1; AJvYcCU0f25awlFvpd9RlYjyP/s72gXSfNM23U5nZZBzpOqGpJkZdm53cevP/vEJ53yn1PNsEtQfEw9ksfzyP7Fe1eW0DgI=@vger.kernel.org, AJvYcCVXZJe9SU2eGM8NednH6ECml85lzHSLsBhpD8VHgptkFQqYiBb7CMnQQzpbF8YVFtNviyFGfrXME5Wr@vger.kernel.org, AJvYcCXKTw80/gsnmX/voLxp7p2pZvYPMve+ao/uCBLeSA9LZTyDgiaLCTV6uUZ0xo8kaKQ9ZeajTSVwelMWYxIz@vger.kernel.org X-Received: by 2002:a05:6102:38d4:b0:4e2:a29d:ecb6 with SMTP id ada2fe7eead31-4e7f60eb70cmr14268555137.1.1750346629165; Thu, 19 Jun 2025 08:23:49 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20250617171957.162145-1-prabhakar.mahadev-lad.rj@bp.renesas.com> In-Reply-To: <20250617171957.162145-1-prabhakar.mahadev-lad.rj@bp.renesas.com> From: Geert Uytterhoeven Date: Thu, 19 Jun 2025 17:23:37 +0200 X-Gmail-Original-Message-ID: X-Gm-Features: Ac12FXwHPFsk05TRosr47sYOkoUYyYdnTZteNgXfR-AJ5EOF9bDc_k4NJOe-IrM Message-ID: Subject: Re: [PATCH v2 0/4] Add initial support for RZ/N2H SoC and EVK To: Prabhakar Cc: Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Biju Das , Fabrizio Castro , Lad Prabhakar Content-Type: text/plain; charset="UTF-8" Hi Prabhakar, On Tue, 17 Jun 2025 at 19:20, Prabhakar wrote: > From: Lad Prabhakar > > This patch series adds initial support for the Renesas RZ/N2H SoC and > the RZ/N2H Evaluation Board (EVK). The series includes: > 1. An initial SoC DTSI for the RZ/N2H SoC, which includes the basic > configuration of the SoC blocks such as EXT CLKs, 4X CA55, SCIF, > CPG, GIC, and ARMv8 Timer. > 2. A new DTSI for the R9A09G087M44 variant of the RZ/N2H SoC, which > features a 4-core configuration. > 3. Refactoring of the RZ/T2H EVK device tree to extract common entries > into a new file, `rzt2h-n2h-evk-common.dtsi`, to reduce > duplication between the RZ/T2H and RZ/N2H EVK device trees. > 4. An initial device tree for the RZ/N2H EVK, which includes > the common entries from the previous step and sets up the board > model and compatible strings. > > Note, > - I've split up this patch from original series [1] to make it easier > to review and apply. > - This patch series applied on top of the series [2]. > > [1] https://lore.kernel.org/all/20250609203656.333138-1-prabhakar.mahadev-lad.rj@bp.renesas.com/ > [2] https://lore.kernel.org/all/20250617162810.154332-1-prabhakar.mahadev-lad.rj@bp.renesas.com/ > > v1->v2: > - Reordered the `l3_ca55` node and renamed it to `L3_CA55` for consistency > - Renamed the file to `rzt2h-n2h-evk-common.dtsi` to better reflect its > purpose. > - Updated model string to "Renesas RZ/N2H EVK Board based on r9a09g087m44" > - Added reviewed-by tag from Geert Thank you, both [2] and this series are good to go, once the updated renesas,rsci DT bindings are accepted. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds