* [PATCH v2 1/3] clk: renesas: r9a09g047: Add clock and reset signals for the GBETH IPs
2025-06-11 6:16 [PATCH v2 0/3] Add support for GBETH IPs found on RZ/G3E SoCs John Madieu
@ 2025-06-11 6:16 ` John Madieu
2025-06-17 15:11 ` Geert Uytterhoeven
2025-06-11 6:16 ` [PATCH v2 2/3] arm64: dts: renesas: r9a09g047: Add GBETH nodes John Madieu
` (2 subsequent siblings)
3 siblings, 1 reply; 19+ messages in thread
From: John Madieu @ 2025-06-11 6:16 UTC (permalink / raw)
To: andrew+netdev, conor+dt, davem, edumazet, geert+renesas, krzk+dt,
kuba, pabeni, prabhakar.mahadev-lad.rj, robh
Cc: biju.das.jz, devicetree, john.madieu, linux-kernel,
linux-renesas-soc, magnus.damm, netdev, John Madieu
Add clock and reset entries for the Gigabit Ethernet Interfaces (GBETH 0-1)
IPs found on the RZ/G3E SoC. This includes various PLLs, dividers, and mux
clocks needed by these two GBETH IPs.
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Tested-by: Biju Das <biju.das.jz@bp.renesas.com>
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---
drivers/clk/renesas/r9a09g047-cpg.c | 64 +++++++++++++++++++++++++++++
1 file changed, 64 insertions(+)
diff --git a/drivers/clk/renesas/r9a09g047-cpg.c b/drivers/clk/renesas/r9a09g047-cpg.c
index 21699999cedd..21352beed3a6 100644
--- a/drivers/clk/renesas/r9a09g047-cpg.c
+++ b/drivers/clk/renesas/r9a09g047-cpg.c
@@ -29,6 +29,7 @@ enum clk_ids {
CLK_PLLDTY,
CLK_PLLCA55,
CLK_PLLVDO,
+ CLK_PLLETH,
/* Internal Core Clocks */
CLK_PLLCM33_DIV3,
@@ -46,6 +47,15 @@ enum clk_ids {
CLK_PLLDTY_ACPU,
CLK_PLLDTY_ACPU_DIV2,
CLK_PLLDTY_ACPU_DIV4,
+ CLK_PLLDTY_DIV8,
+ CLK_PLLETH_DIV_250_FIX,
+ CLK_PLLETH_DIV_125_FIX,
+ CLK_CSDIV_PLLETH_GBE0,
+ CLK_CSDIV_PLLETH_GBE1,
+ CLK_SMUX2_GBE0_TXCLK,
+ CLK_SMUX2_GBE0_RXCLK,
+ CLK_SMUX2_GBE1_TXCLK,
+ CLK_SMUX2_GBE1_RXCLK,
CLK_PLLDTY_DIV16,
CLK_PLLVDO_CRU0,
CLK_PLLVDO_GPU,
@@ -85,7 +95,18 @@ static const struct clk_div_table dtable_2_64[] = {
{0, 0},
};
+static const struct clk_div_table dtable_2_100[] = {
+ {0, 2},
+ {1, 10},
+ {2, 100},
+ {0, 0},
+};
+
/* Mux clock tables */
+static const char * const smux2_gbe0_rxclk[] = { ".plleth_gbe0", "et0_rxc_rx_clk" };
+static const char * const smux2_gbe0_txclk[] = { ".plleth_gbe0", "et0_txc_tx_clk" };
+static const char * const smux2_gbe1_rxclk[] = { ".plleth_gbe1", "et1-rxc-rx_clk" };
+static const char * const smux2_gbe1_txclk[] = { ".plleth_gbe1", "et1-txc-tx_clk" };
static const char * const smux2_xspi_clk0[] = { ".pllcm33_div3", ".pllcm33_div4" };
static const char * const smux2_xspi_clk1[] = { ".smux2_xspi_clk0", ".pllcm33_div5" };
@@ -100,6 +121,7 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
DEF_FIXED(".pllcln", CLK_PLLCLN, CLK_QEXTAL, 200, 3),
DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3),
DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLLCA55),
+ DEF_FIXED(".plleth", CLK_PLLETH, CLK_QEXTAL, 125, 3),
DEF_FIXED(".pllvdo", CLK_PLLVDO, CLK_QEXTAL, 105, 2),
/* Internal Core Clocks */
@@ -122,6 +144,18 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dtable_2_64),
DEF_FIXED(".plldty_acpu_div2", CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU, 1, 2),
DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4),
+ DEF_FIXED(".plldty_div8", CLK_PLLDTY_DIV8, CLK_PLLDTY, 1, 8),
+
+ DEF_FIXED(".plleth_250_fix", CLK_PLLETH_DIV_250_FIX, CLK_PLLETH, 1, 4),
+ DEF_FIXED(".plleth_125_fix", CLK_PLLETH_DIV_125_FIX, CLK_PLLETH_DIV_250_FIX, 1, 2),
+ DEF_CSDIV(".plleth_gbe0", CLK_CSDIV_PLLETH_GBE0, CLK_PLLETH_DIV_250_FIX,
+ CSDIV0_DIVCTL0, dtable_2_100),
+ DEF_CSDIV(".plleth_gbe1", CLK_CSDIV_PLLETH_GBE1, CLK_PLLETH_DIV_250_FIX,
+ CSDIV0_DIVCTL1, dtable_2_100),
+ DEF_SMUX(".smux2_gbe0_txclk", CLK_SMUX2_GBE0_TXCLK, SSEL0_SELCTL2, smux2_gbe0_txclk),
+ DEF_SMUX(".smux2_gbe0_rxclk", CLK_SMUX2_GBE0_RXCLK, SSEL0_SELCTL3, smux2_gbe0_rxclk),
+ DEF_SMUX(".smux2_gbe1_txclk", CLK_SMUX2_GBE1_TXCLK, SSEL1_SELCTL0, smux2_gbe1_txclk),
+ DEF_SMUX(".smux2_gbe1_rxclk", CLK_SMUX2_GBE1_RXCLK, SSEL1_SELCTL1, smux2_gbe1_rxclk),
DEF_FIXED(".plldty_div16", CLK_PLLDTY_DIV16, CLK_PLLDTY, 1, 16),
DEF_DDIV(".pllvdo_cru0", CLK_PLLVDO_CRU0, CLK_PLLVDO, CDDIV3_DIVCTL3, dtable_2_4),
@@ -139,6 +173,10 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
CDDIV1_DIVCTL3, dtable_1_8),
DEF_FIXED("iotop_0_shclk", R9A09G047_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1),
DEF_FIXED("spi_clk_spi", R9A09G047_SPI_CLK_SPI, CLK_PLLCM33_XSPI, 1, 2),
+ DEF_FIXED("gbeth_0_clk_ptp_ref_i", R9A09G047_GBETH_0_CLK_PTP_REF_I,
+ CLK_PLLETH_DIV_125_FIX, 1, 1),
+ DEF_FIXED("gbeth_1_clk_ptp_ref_i", R9A09G047_GBETH_1_CLK_PTP_REF_I,
+ CLK_PLLETH_DIV_125_FIX, 1, 1),
};
static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
@@ -214,6 +252,30 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
BUS_MSTOP(8, BIT(4))),
DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14,
BUS_MSTOP(8, BIT(4))),
+ DEF_MOD("gbeth_0_clk_tx_i", CLK_SMUX2_GBE0_TXCLK, 11, 8, 5, 24,
+ BUS_MSTOP(8, BIT(5))),
+ DEF_MOD("gbeth_0_clk_rx_i", CLK_SMUX2_GBE0_RXCLK, 11, 9, 5, 25,
+ BUS_MSTOP(8, BIT(5))),
+ DEF_MOD("gbeth_0_clk_tx_180_i", CLK_SMUX2_GBE0_TXCLK, 11, 10, 5, 26,
+ BUS_MSTOP(8, BIT(5))),
+ DEF_MOD("gbeth_0_clk_rx_180_i", CLK_SMUX2_GBE0_RXCLK, 11, 11, 5, 27,
+ BUS_MSTOP(8, BIT(5))),
+ DEF_MOD("gbeth_0_aclk_csr_i", CLK_PLLDTY_DIV8, 11, 12, 5, 28,
+ BUS_MSTOP(8, BIT(5))),
+ DEF_MOD("gbeth_0_aclk_i", CLK_PLLDTY_DIV8, 11, 13, 5, 29,
+ BUS_MSTOP(8, BIT(5))),
+ DEF_MOD("gbeth_1_clk_tx_i", CLK_SMUX2_GBE1_TXCLK, 11, 14, 5, 30,
+ BUS_MSTOP(8, BIT(6))),
+ DEF_MOD("gbeth_1_clk_rx_i", CLK_SMUX2_GBE1_RXCLK, 11, 15, 5, 31,
+ BUS_MSTOP(8, BIT(6))),
+ DEF_MOD("gbeth_1_clk_tx_180_i", CLK_SMUX2_GBE1_TXCLK, 12, 0, 6, 0,
+ BUS_MSTOP(8, BIT(6))),
+ DEF_MOD("gbeth_1_clk_rx_180_i", CLK_SMUX2_GBE1_RXCLK, 12, 1, 6, 1,
+ BUS_MSTOP(8, BIT(6))),
+ DEF_MOD("gbeth_1_aclk_csr_i", CLK_PLLDTY_DIV8, 12, 2, 6, 2,
+ BUS_MSTOP(8, BIT(6))),
+ DEF_MOD("gbeth_1_aclk_i", CLK_PLLDTY_DIV8, 12, 3, 6, 3,
+ BUS_MSTOP(8, BIT(6))),
DEF_MOD("cru_0_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18,
BUS_MSTOP(9, BIT(4))),
DEF_MOD_NO_PM("cru_0_vclk", CLK_PLLVDO_CRU0, 13, 3, 6, 19,
@@ -255,6 +317,8 @@ static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
DEF_RST(10, 7, 4, 24), /* SDHI_0_IXRST */
DEF_RST(10, 8, 4, 25), /* SDHI_1_IXRST */
DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */
+ DEF_RST(11, 0, 5, 1), /* GBETH_0_ARESETN_I */
+ DEF_RST(11, 1, 5, 2), /* GBETH_1_ARESETN_I */
DEF_RST(12, 5, 5, 22), /* CRU_0_PRESETN */
DEF_RST(12, 6, 5, 23), /* CRU_0_ARESETN */
DEF_RST(12, 7, 5, 24), /* CRU_0_S_RESETN */
--
2.25.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [PATCH v2 1/3] clk: renesas: r9a09g047: Add clock and reset signals for the GBETH IPs
2025-06-11 6:16 ` [PATCH v2 1/3] clk: renesas: r9a09g047: Add clock and reset signals for the GBETH IPs John Madieu
@ 2025-06-17 15:11 ` Geert Uytterhoeven
2025-06-18 10:04 ` John Madieu
0 siblings, 1 reply; 19+ messages in thread
From: Geert Uytterhoeven @ 2025-06-17 15:11 UTC (permalink / raw)
To: John Madieu
Cc: andrew+netdev, conor+dt, davem, edumazet, krzk+dt, kuba, pabeni,
prabhakar.mahadev-lad.rj, robh, biju.das.jz, devicetree,
john.madieu, linux-kernel, linux-renesas-soc, magnus.damm, netdev
Hi John,
On Wed, 11 Jun 2025 at 11:02, John Madieu <john.madieu.xa@bp.renesas.com> wrote:
> Add clock and reset entries for the Gigabit Ethernet Interfaces (GBETH 0-1)
> IPs found on the RZ/G3E SoC. This includes various PLLs, dividers, and mux
> clocks needed by these two GBETH IPs.
>
> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> Tested-by: Biju Das <biju.das.jz@bp.renesas.com>
> Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
Thanks for your patch!
> --- a/drivers/clk/renesas/r9a09g047-cpg.c
> +++ b/drivers/clk/renesas/r9a09g047-cpg.c
> @@ -85,7 +95,18 @@ static const struct clk_div_table dtable_2_64[] = {
> {0, 0},
> };
>
> +static const struct clk_div_table dtable_2_100[] = {
> + {0, 2},
> + {1, 10},
> + {2, 100},
> + {0, 0},
> +};
> +
> /* Mux clock tables */
> +static const char * const smux2_gbe0_rxclk[] = { ".plleth_gbe0", "et0_rxc_rx_clk" };
> +static const char * const smux2_gbe0_txclk[] = { ".plleth_gbe0", "et0_txc_tx_clk" };
> +static const char * const smux2_gbe1_rxclk[] = { ".plleth_gbe1", "et1-rxc-rx_clk" };
> +static const char * const smux2_gbe1_txclk[] = { ".plleth_gbe1", "et1-txc-tx_clk" };
Please use consistent naming for the external clocks (underscores
vs. dashes). However, both differ from the similar names used on
RZ/V2H and RZ/V2N; perhaps use the naming from the latter instead?
> static const char * const smux2_xspi_clk0[] = { ".pllcm33_div3", ".pllcm33_div4" };
> static const char * const smux2_xspi_clk1[] = { ".smux2_xspi_clk0", ".pllcm33_div5" };
>
> @@ -214,6 +252,30 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
> BUS_MSTOP(8, BIT(4))),
> DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14,
> BUS_MSTOP(8, BIT(4))),
> + DEF_MOD("gbeth_0_clk_tx_i", CLK_SMUX2_GBE0_TXCLK, 11, 8, 5, 24,
> + BUS_MSTOP(8, BIT(5))),
> + DEF_MOD("gbeth_0_clk_rx_i", CLK_SMUX2_GBE0_RXCLK, 11, 9, 5, 25,
> + BUS_MSTOP(8, BIT(5))),
> + DEF_MOD("gbeth_0_clk_tx_180_i", CLK_SMUX2_GBE0_TXCLK, 11, 10, 5, 26,
> + BUS_MSTOP(8, BIT(5))),
> + DEF_MOD("gbeth_0_clk_rx_180_i", CLK_SMUX2_GBE0_RXCLK, 11, 11, 5, 27,
> + BUS_MSTOP(8, BIT(5))),
> + DEF_MOD("gbeth_0_aclk_csr_i", CLK_PLLDTY_DIV8, 11, 12, 5, 28,
> + BUS_MSTOP(8, BIT(5))),
> + DEF_MOD("gbeth_0_aclk_i", CLK_PLLDTY_DIV8, 11, 13, 5, 29,
> + BUS_MSTOP(8, BIT(5))),
> + DEF_MOD("gbeth_1_clk_tx_i", CLK_SMUX2_GBE1_TXCLK, 11, 14, 5, 30,
> + BUS_MSTOP(8, BIT(6))),
> + DEF_MOD("gbeth_1_clk_rx_i", CLK_SMUX2_GBE1_RXCLK, 11, 15, 5, 31,
> + BUS_MSTOP(8, BIT(6))),
> + DEF_MOD("gbeth_1_clk_tx_180_i", CLK_SMUX2_GBE1_TXCLK, 12, 0, 6, 0,
scripts/checkpatch.pl says:
WARNING: please, no space before tabs
> + BUS_MSTOP(8, BIT(6))),
> + DEF_MOD("gbeth_1_clk_rx_180_i", CLK_SMUX2_GBE1_RXCLK, 12, 1, 6, 1,
> + BUS_MSTOP(8, BIT(6))),
> + DEF_MOD("gbeth_1_aclk_csr_i", CLK_PLLDTY_DIV8, 12, 2, 6, 2,
> + BUS_MSTOP(8, BIT(6))),
> + DEF_MOD("gbeth_1_aclk_i", CLK_PLLDTY_DIV8, 12, 3, 6, 3,
> + BUS_MSTOP(8, BIT(6))),
Shouldn't all of these use DEF_MOD_MUX_EXTERNAL() instead of DEF_MOD(),
like on RZ/V2H and RZ/V2N?
> DEF_MOD("cru_0_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18,
> BUS_MSTOP(9, BIT(4))),
> DEF_MOD_NO_PM("cru_0_vclk", CLK_PLLVDO_CRU0, 13, 3, 6, 19,
The rest LGTM. Note that I don't have access to the Additional Document,
so I couldn't verify all details.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 19+ messages in thread* RE: [PATCH v2 1/3] clk: renesas: r9a09g047: Add clock and reset signals for the GBETH IPs
2025-06-17 15:11 ` Geert Uytterhoeven
@ 2025-06-18 10:04 ` John Madieu
2025-06-18 11:02 ` Geert Uytterhoeven
0 siblings, 1 reply; 19+ messages in thread
From: John Madieu @ 2025-06-18 10:04 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: andrew+netdev@lunn.ch, conor+dt@kernel.org, davem@davemloft.net,
edumazet@google.com, krzk+dt@kernel.org, kuba@kernel.org,
pabeni@redhat.com, Prabhakar Mahadev Lad, robh@kernel.org,
Biju Das, devicetree@vger.kernel.org, john.madieu@gmail.com,
linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
magnus.damm@gmail.com, netdev@vger.kernel.org
Hi Geert,
Thanks for your review.
> -----Original Message-----
> From: Geert Uytterhoeven <geert@linux-m68k.org>
> Sent: Tuesday, June 17, 2025 5:11 PM
> To: John Madieu <john.madieu.xa@bp.renesas.com>
> Subject: Re: [PATCH v2 1/3] clk: renesas: r9a09g047: Add clock and reset
> signals for the GBETH IPs
>
> Hi John,
>
> On Wed, 11 Jun 2025 at 11:02, John Madieu <john.madieu.xa@bp.renesas.com>
> wrote:
> > Add clock and reset entries for the Gigabit Ethernet Interfaces (GBETH
> > 0-1) IPs found on the RZ/G3E SoC. This includes various PLLs,
> > dividers, and mux clocks needed by these two GBETH IPs.
> >
> > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> > Tested-by: Biju Das <biju.das.jz@bp.renesas.com>
> > Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
>
> Thanks for your patch!
>
> > --- a/drivers/clk/renesas/r9a09g047-cpg.c
> > +++ b/drivers/clk/renesas/r9a09g047-cpg.c
> > @@ -85,7 +95,18 @@ static const struct clk_div_table dtable_2_64[] = {
> > {0, 0},
> > };
> >
> > +static const struct clk_div_table dtable_2_100[] = {
> > + {0, 2},
> > + {1, 10},
> > + {2, 100},
> > + {0, 0},
> > +};
> > +
> > /* Mux clock tables */
> > +static const char * const smux2_gbe0_rxclk[] = { ".plleth_gbe0",
> > +"et0_rxc_rx_clk" }; static const char * const smux2_gbe0_txclk[] = {
> > +".plleth_gbe0", "et0_txc_tx_clk" }; static const char * const
> > +smux2_gbe1_rxclk[] = { ".plleth_gbe1", "et1-rxc-rx_clk" }; static
> > +const char * const smux2_gbe1_txclk[] = { ".plleth_gbe1",
> > +"et1-txc-tx_clk" };
>
> Please use consistent naming for the external clocks (underscores vs.
> dashes). However, both differ from the similar names used on RZ/V2H and
> RZ/V2N; perhaps use the naming from the latter instead?
>
Noted.
> > static const char * const smux2_xspi_clk0[] = { ".pllcm33_div3",
> > ".pllcm33_div4" }; static const char * const smux2_xspi_clk1[] = {
> > ".smux2_xspi_clk0", ".pllcm33_div5" };
> >
>
> > @@ -214,6 +252,30 @@ static const struct rzv2h_mod_clk
> r9a09g047_mod_clks[] __initconst = {
> > BUS_MSTOP(8, BIT(4))),
> > DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4,
> 10, 14, 5, 14,
> > BUS_MSTOP(8, BIT(4))),
> > + DEF_MOD("gbeth_0_clk_tx_i", CLK_SMUX2_GBE0_TXCLK,
> 11, 8, 5, 24,
> > + BUS_MSTOP(8, BIT(5))),
> > + DEF_MOD("gbeth_0_clk_rx_i", CLK_SMUX2_GBE0_RXCLK,
> 11, 9, 5, 25,
> > + BUS_MSTOP(8, BIT(5))),
> > + DEF_MOD("gbeth_0_clk_tx_180_i", CLK_SMUX2_GBE0_TXCLK,
> 11, 10, 5, 26,
> > + BUS_MSTOP(8, BIT(5))),
> > + DEF_MOD("gbeth_0_clk_rx_180_i", CLK_SMUX2_GBE0_RXCLK,
> 11, 11, 5, 27,
> > + BUS_MSTOP(8, BIT(5))),
> > + DEF_MOD("gbeth_0_aclk_csr_i", CLK_PLLDTY_DIV8, 11, 12,
> 5, 28,
> > + BUS_MSTOP(8, BIT(5))),
> > + DEF_MOD("gbeth_0_aclk_i", CLK_PLLDTY_DIV8, 11, 13,
> 5, 29,
> > + BUS_MSTOP(8, BIT(5))),
> > + DEF_MOD("gbeth_1_clk_tx_i", CLK_SMUX2_GBE1_TXCLK,
> 11, 14, 5, 30,
> > + BUS_MSTOP(8, BIT(6))),
> > + DEF_MOD("gbeth_1_clk_rx_i", CLK_SMUX2_GBE1_RXCLK,
> 11, 15, 5, 31,
> > + BUS_MSTOP(8, BIT(6))),
> > + DEF_MOD("gbeth_1_clk_tx_180_i", CLK_SMUX2_GBE1_TXCLK,
> 12, 0, 6, 0,
>
> scripts/checkpatch.pl says:
>
> WARNING: please, no space before tabs
>
Noted.
> > + BUS_MSTOP(8, BIT(6))),
> > + DEF_MOD("gbeth_1_clk_rx_180_i", CLK_SMUX2_GBE1_RXCLK,
> 12, 1, 6, 1,
> > + BUS_MSTOP(8, BIT(6))),
> > + DEF_MOD("gbeth_1_aclk_csr_i", CLK_PLLDTY_DIV8, 12, 2,
> 6, 2,
> > + BUS_MSTOP(8, BIT(6))),
> > + DEF_MOD("gbeth_1_aclk_i", CLK_PLLDTY_DIV8, 12, 3,
> 6, 3,
> > + BUS_MSTOP(8, BIT(6))),
>
> Shouldn't all of these use DEF_MOD_MUX_EXTERNAL() instead of DEF_MOD(),
> like on RZ/V2H and RZ/V2N?
>
Do we really need to use DEF_MOD_MUX_EXTERNAL? Unlike for the RZ/V2H,
On G3E, unbind/bind works with DEF_MOD. I can however switch to
DEF_MOD_MUX_EXTERNAL for consistency if required.
Please let me know.
> > DEF_MOD("cru_0_aclk", CLK_PLLDTY_ACPU_DIV2,
> 13, 2, 6, 18,
> > BUS_MSTOP(9, BIT(4))),
> > DEF_MOD_NO_PM("cru_0_vclk", CLK_PLLVDO_CRU0, 13, 3,
> 6, 19,
>
> The rest LGTM. Note that I don't have access to the Additional Document,
> so I couldn't verify all details.
>
> Gr{oetje,eeting}s,
>
> Geert
>
Regards,
John
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-
> m68k.org
>
> In personal conversations with technical people, I call myself a hacker.
> But when I'm talking to journalists I just say "programmer" or something
> like that.
> -- Linus Torvalds
^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [PATCH v2 1/3] clk: renesas: r9a09g047: Add clock and reset signals for the GBETH IPs
2025-06-18 10:04 ` John Madieu
@ 2025-06-18 11:02 ` Geert Uytterhoeven
2025-06-19 4:34 ` John Madieu
0 siblings, 1 reply; 19+ messages in thread
From: Geert Uytterhoeven @ 2025-06-18 11:02 UTC (permalink / raw)
To: John Madieu
Cc: andrew+netdev@lunn.ch, conor+dt@kernel.org, davem@davemloft.net,
edumazet@google.com, krzk+dt@kernel.org, kuba@kernel.org,
pabeni@redhat.com, Prabhakar Mahadev Lad, robh@kernel.org,
Biju Das, devicetree@vger.kernel.org, john.madieu@gmail.com,
linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
magnus.damm@gmail.com, netdev@vger.kernel.org
Hi John,
On Wed, 18 Jun 2025 at 12:04, John Madieu <john.madieu.xa@bp.renesas.com> wrote:
> > From: Geert Uytterhoeven <geert@linux-m68k.org>
> > On Wed, 11 Jun 2025 at 11:02, John Madieu <john.madieu.xa@bp.renesas.com>
> > wrote:
> > > Add clock and reset entries for the Gigabit Ethernet Interfaces (GBETH
> > > 0-1) IPs found on the RZ/G3E SoC. This includes various PLLs,
> > > dividers, and mux clocks needed by these two GBETH IPs.
> > >
> > > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > Tested-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
> >
> > Thanks for your patch!
> >
> > > --- a/drivers/clk/renesas/r9a09g047-cpg.c
> > > +++ b/drivers/clk/renesas/r9a09g047-cpg.c
> > > @@ -214,6 +252,30 @@ static const struct rzv2h_mod_clk
> > r9a09g047_mod_clks[] __initconst = {
> > > BUS_MSTOP(8, BIT(4))),
> > > DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4,
> > 10, 14, 5, 14,
> > > BUS_MSTOP(8, BIT(4))),
> > > + DEF_MOD("gbeth_0_clk_tx_i", CLK_SMUX2_GBE0_TXCLK,
> > 11, 8, 5, 24,
> > > + BUS_MSTOP(8, BIT(5))),
> > > + DEF_MOD("gbeth_0_clk_rx_i", CLK_SMUX2_GBE0_RXCLK,
> > 11, 9, 5, 25,
> > > + BUS_MSTOP(8, BIT(5))),
> > > + DEF_MOD("gbeth_0_clk_tx_180_i", CLK_SMUX2_GBE0_TXCLK,
> > 11, 10, 5, 26,
> > > + BUS_MSTOP(8, BIT(5))),
> > > + DEF_MOD("gbeth_0_clk_rx_180_i", CLK_SMUX2_GBE0_RXCLK,
> > 11, 11, 5, 27,
> > > + BUS_MSTOP(8, BIT(5))),
> > > + DEF_MOD("gbeth_0_aclk_csr_i", CLK_PLLDTY_DIV8, 11, 12,
> > 5, 28,
> > > + BUS_MSTOP(8, BIT(5))),
> > > + DEF_MOD("gbeth_0_aclk_i", CLK_PLLDTY_DIV8, 11, 13,
> > 5, 29,
> > > + BUS_MSTOP(8, BIT(5))),
> > > + DEF_MOD("gbeth_1_clk_tx_i", CLK_SMUX2_GBE1_TXCLK,
> > 11, 14, 5, 30,
> > > + BUS_MSTOP(8, BIT(6))),
> > > + DEF_MOD("gbeth_1_clk_rx_i", CLK_SMUX2_GBE1_RXCLK,
> > 11, 15, 5, 31,
> > > + BUS_MSTOP(8, BIT(6))),
> > > + DEF_MOD("gbeth_1_clk_tx_180_i", CLK_SMUX2_GBE1_TXCLK,
> > 12, 0, 6, 0,
> >
> > scripts/checkpatch.pl says:
> >
> > WARNING: please, no space before tabs
> >
>
> Noted.
>
> > > + BUS_MSTOP(8, BIT(6))),
> > > + DEF_MOD("gbeth_1_clk_rx_180_i", CLK_SMUX2_GBE1_RXCLK,
> > 12, 1, 6, 1,
> > > + BUS_MSTOP(8, BIT(6))),
> > > + DEF_MOD("gbeth_1_aclk_csr_i", CLK_PLLDTY_DIV8, 12, 2,
> > 6, 2,
> > > + BUS_MSTOP(8, BIT(6))),
> > > + DEF_MOD("gbeth_1_aclk_i", CLK_PLLDTY_DIV8, 12, 3,
> > 6, 3,
> > > + BUS_MSTOP(8, BIT(6))),
> >
> > Shouldn't all of these use DEF_MOD_MUX_EXTERNAL() instead of DEF_MOD(),
> > like on RZ/V2H and RZ/V2N?
> >
>
> Do we really need to use DEF_MOD_MUX_EXTERNAL? Unlike for the RZ/V2H,
> On G3E, unbind/bind works with DEF_MOD. I can however switch to
> DEF_MOD_MUX_EXTERNAL for consistency if required.
>
> Please let me know.
Does that mean the monitor bits on RZ/G3E do reflect the correct state of
external clocks? If yes, then DEF_MOD() is fine.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 19+ messages in thread* RE: [PATCH v2 1/3] clk: renesas: r9a09g047: Add clock and reset signals for the GBETH IPs
2025-06-18 11:02 ` Geert Uytterhoeven
@ 2025-06-19 4:34 ` John Madieu
2025-06-19 8:21 ` Lad, Prabhakar
0 siblings, 1 reply; 19+ messages in thread
From: John Madieu @ 2025-06-19 4:34 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: andrew+netdev@lunn.ch, conor+dt@kernel.org, davem@davemloft.net,
edumazet@google.com, krzk+dt@kernel.org, kuba@kernel.org,
pabeni@redhat.com, Prabhakar Mahadev Lad, robh@kernel.org,
Biju Das, devicetree@vger.kernel.org, john.madieu@gmail.com,
linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
magnus.damm@gmail.com, netdev@vger.kernel.org
Hi Geert,
> -----Original Message-----
> From: Geert Uytterhoeven <geert@linux-m68k.org>
> Sent: Wednesday, June 18, 2025 1:02 PM
> To: John Madieu <john.madieu.xa@bp.renesas.com>
> Subject: Re: [PATCH v2 1/3] clk: renesas: r9a09g047: Add clock and reset
> signals for the GBETH IPs
>
> Hi John,
>
> On Wed, 18 Jun 2025 at 12:04, John Madieu <john.madieu.xa@bp.renesas.com>
> wrote:
> > > From: Geert Uytterhoeven <geert@linux-m68k.org> On Wed, 11 Jun 2025
> > > at 11:02, John Madieu <john.madieu.xa@bp.renesas.com>
> > > wrote:
> > > > Add clock and reset entries for the Gigabit Ethernet Interfaces
> > > > (GBETH
> > > > 0-1) IPs found on the RZ/G3E SoC. This includes various PLLs,
> > > > dividers, and mux clocks needed by these two GBETH IPs.
> > > >
> > > > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > > Tested-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > > Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
> > >
> > > Thanks for your patch!
> > >
> > > > --- a/drivers/clk/renesas/r9a09g047-cpg.c
> > > > +++ b/drivers/clk/renesas/r9a09g047-cpg.c
>
> > > > @@ -214,6 +252,30 @@ static const struct rzv2h_mod_clk
> > > r9a09g047_mod_clks[] __initconst = {
> > > > BUS_MSTOP(8,
> BIT(4))),
> > > > DEF_MOD("sdhi_2_aclk",
> CLK_PLLDTY_ACPU_DIV4,
> > > 10, 14, 5, 14,
> > > > BUS_MSTOP(8,
> > > > BIT(4))),
> > > > + DEF_MOD("gbeth_0_clk_tx_i",
> CLK_SMUX2_GBE0_TXCLK,
> > > 11, 8, 5, 24,
> > > > + BUS_MSTOP(8,
> BIT(5))),
> > > > + DEF_MOD("gbeth_0_clk_rx_i",
> CLK_SMUX2_GBE0_RXCLK,
> > > 11, 9, 5, 25,
> > > > + BUS_MSTOP(8,
> BIT(5))),
> > > > + DEF_MOD("gbeth_0_clk_tx_180_i",
> CLK_SMUX2_GBE0_TXCLK,
> > > 11, 10, 5, 26,
> > > > + BUS_MSTOP(8,
> BIT(5))),
> > > > + DEF_MOD("gbeth_0_clk_rx_180_i",
> CLK_SMUX2_GBE0_RXCLK,
> > > 11, 11, 5, 27,
> > > > + BUS_MSTOP(8,
> BIT(5))),
> > > > + DEF_MOD("gbeth_0_aclk_csr_i", CLK_PLLDTY_DIV8, 11,
> 12,
> > > 5, 28,
> > > > + BUS_MSTOP(8,
> BIT(5))),
> > > > + DEF_MOD("gbeth_0_aclk_i", CLK_PLLDTY_DIV8, 11,
> 13,
> > > 5, 29,
> > > > + BUS_MSTOP(8,
> BIT(5))),
> > > > + DEF_MOD("gbeth_1_clk_tx_i",
> CLK_SMUX2_GBE1_TXCLK,
> > > 11, 14, 5, 30,
> > > > + BUS_MSTOP(8,
> BIT(6))),
> > > > + DEF_MOD("gbeth_1_clk_rx_i",
> CLK_SMUX2_GBE1_RXCLK,
> > > 11, 15, 5, 31,
> > > > + BUS_MSTOP(8,
> BIT(6))),
> > > > + DEF_MOD("gbeth_1_clk_tx_180_i",
> CLK_SMUX2_GBE1_TXCLK,
> > > 12, 0, 6, 0,
> > >
> > > scripts/checkpatch.pl says:
> > >
> > > WARNING: please, no space before tabs
> > >
> >
> > Noted.
> >
> > > > + BUS_MSTOP(8,
> BIT(6))),
> > > > + DEF_MOD("gbeth_1_clk_rx_180_i",
> CLK_SMUX2_GBE1_RXCLK,
> > > 12, 1, 6, 1,
> > > > + BUS_MSTOP(8,
> BIT(6))),
> > > > + DEF_MOD("gbeth_1_aclk_csr_i", CLK_PLLDTY_DIV8, 12,
> 2,
> > > 6, 2,
> > > > + BUS_MSTOP(8,
> BIT(6))),
> > > > + DEF_MOD("gbeth_1_aclk_i", CLK_PLLDTY_DIV8, 12,
> 3,
> > > 6, 3,
> > > > + BUS_MSTOP(8,
> > > > + BIT(6))),
> > >
> > > Shouldn't all of these use DEF_MOD_MUX_EXTERNAL() instead of
> > > DEF_MOD(), like on RZ/V2H and RZ/V2N?
> > >
> >
> > Do we really need to use DEF_MOD_MUX_EXTERNAL? Unlike for the RZ/V2H,
> > On G3E, unbind/bind works with DEF_MOD. I can however switch to
> > DEF_MOD_MUX_EXTERNAL for consistency if required.
> >
> > Please let me know.
>
> Does that mean the monitor bits on RZ/G3E do reflect the correct state of
> external clocks? If yes, then DEF_MOD() is fine.
>
> Gr{oetje,eeting}s,
>
> Geert
>
Checked DEF_MOD() and had expected result. I'll then it and send v3.
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-
> m68k.org
Regards,
John
>
> In personal conversations with technical people, I call myself a hacker.
> But when I'm talking to journalists I just say "programmer" or something
> like that.
> -- Linus Torvalds
^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [PATCH v2 1/3] clk: renesas: r9a09g047: Add clock and reset signals for the GBETH IPs
2025-06-19 4:34 ` John Madieu
@ 2025-06-19 8:21 ` Lad, Prabhakar
2025-06-25 15:18 ` Geert Uytterhoeven
0 siblings, 1 reply; 19+ messages in thread
From: Lad, Prabhakar @ 2025-06-19 8:21 UTC (permalink / raw)
To: John Madieu
Cc: Geert Uytterhoeven, andrew+netdev@lunn.ch, conor+dt@kernel.org,
davem@davemloft.net, edumazet@google.com, krzk+dt@kernel.org,
kuba@kernel.org, pabeni@redhat.com, Prabhakar Mahadev Lad,
robh@kernel.org, Biju Das, devicetree@vger.kernel.org,
john.madieu@gmail.com, linux-kernel@vger.kernel.org,
linux-renesas-soc@vger.kernel.org, magnus.damm@gmail.com,
netdev@vger.kernel.org
Hi John,
On Thu, Jun 19, 2025 at 5:34 AM John Madieu
<john.madieu.xa@bp.renesas.com> wrote:
>
> Hi Geert,
>
> > -----Original Message-----
> > From: Geert Uytterhoeven <geert@linux-m68k.org>
> > Sent: Wednesday, June 18, 2025 1:02 PM
> > To: John Madieu <john.madieu.xa@bp.renesas.com>
> > Subject: Re: [PATCH v2 1/3] clk: renesas: r9a09g047: Add clock and reset
> > signals for the GBETH IPs
> >
> > Hi John,
> >
> > On Wed, 18 Jun 2025 at 12:04, John Madieu <john.madieu.xa@bp.renesas.com>
> > wrote:
> > > > From: Geert Uytterhoeven <geert@linux-m68k.org> On Wed, 11 Jun 2025
> > > > at 11:02, John Madieu <john.madieu.xa@bp.renesas.com>
> > > > wrote:
> > > > > Add clock and reset entries for the Gigabit Ethernet Interfaces
> > > > > (GBETH
> > > > > 0-1) IPs found on the RZ/G3E SoC. This includes various PLLs,
> > > > > dividers, and mux clocks needed by these two GBETH IPs.
> > > > >
> > > > > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > > > Tested-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > > > Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
> > > >
> > > > Thanks for your patch!
> > > >
> > > > > --- a/drivers/clk/renesas/r9a09g047-cpg.c
> > > > > +++ b/drivers/clk/renesas/r9a09g047-cpg.c
> >
> > > > > @@ -214,6 +252,30 @@ static const struct rzv2h_mod_clk
> > > > r9a09g047_mod_clks[] __initconst = {
> > > > > BUS_MSTOP(8,
> > BIT(4))),
> > > > > DEF_MOD("sdhi_2_aclk",
> > CLK_PLLDTY_ACPU_DIV4,
> > > > 10, 14, 5, 14,
> > > > > BUS_MSTOP(8,
> > > > > BIT(4))),
> > > > > + DEF_MOD("gbeth_0_clk_tx_i",
> > CLK_SMUX2_GBE0_TXCLK,
> > > > 11, 8, 5, 24,
> > > > > + BUS_MSTOP(8,
> > BIT(5))),
> > > > > + DEF_MOD("gbeth_0_clk_rx_i",
> > CLK_SMUX2_GBE0_RXCLK,
> > > > 11, 9, 5, 25,
> > > > > + BUS_MSTOP(8,
> > BIT(5))),
> > > > > + DEF_MOD("gbeth_0_clk_tx_180_i",
> > CLK_SMUX2_GBE0_TXCLK,
> > > > 11, 10, 5, 26,
> > > > > + BUS_MSTOP(8,
> > BIT(5))),
> > > > > + DEF_MOD("gbeth_0_clk_rx_180_i",
> > CLK_SMUX2_GBE0_RXCLK,
> > > > 11, 11, 5, 27,
> > > > > + BUS_MSTOP(8,
> > BIT(5))),
> > > > > + DEF_MOD("gbeth_0_aclk_csr_i", CLK_PLLDTY_DIV8, 11,
> > 12,
> > > > 5, 28,
> > > > > + BUS_MSTOP(8,
> > BIT(5))),
> > > > > + DEF_MOD("gbeth_0_aclk_i", CLK_PLLDTY_DIV8, 11,
> > 13,
> > > > 5, 29,
> > > > > + BUS_MSTOP(8,
> > BIT(5))),
> > > > > + DEF_MOD("gbeth_1_clk_tx_i",
> > CLK_SMUX2_GBE1_TXCLK,
> > > > 11, 14, 5, 30,
> > > > > + BUS_MSTOP(8,
> > BIT(6))),
> > > > > + DEF_MOD("gbeth_1_clk_rx_i",
> > CLK_SMUX2_GBE1_RXCLK,
> > > > 11, 15, 5, 31,
> > > > > + BUS_MSTOP(8,
> > BIT(6))),
> > > > > + DEF_MOD("gbeth_1_clk_tx_180_i",
> > CLK_SMUX2_GBE1_TXCLK,
> > > > 12, 0, 6, 0,
> > > >
> > > > scripts/checkpatch.pl says:
> > > >
> > > > WARNING: please, no space before tabs
> > > >
> > >
> > > Noted.
> > >
> > > > > + BUS_MSTOP(8,
> > BIT(6))),
> > > > > + DEF_MOD("gbeth_1_clk_rx_180_i",
> > CLK_SMUX2_GBE1_RXCLK,
> > > > 12, 1, 6, 1,
> > > > > + BUS_MSTOP(8,
> > BIT(6))),
> > > > > + DEF_MOD("gbeth_1_aclk_csr_i", CLK_PLLDTY_DIV8, 12,
> > 2,
> > > > 6, 2,
> > > > > + BUS_MSTOP(8,
> > BIT(6))),
> > > > > + DEF_MOD("gbeth_1_aclk_i", CLK_PLLDTY_DIV8, 12,
> > 3,
> > > > 6, 3,
> > > > > + BUS_MSTOP(8,
> > > > > + BIT(6))),
> > > >
> > > > Shouldn't all of these use DEF_MOD_MUX_EXTERNAL() instead of
> > > > DEF_MOD(), like on RZ/V2H and RZ/V2N?
> > > >
> > >
> > > Do we really need to use DEF_MOD_MUX_EXTERNAL? Unlike for the RZ/V2H,
> > > On G3E, unbind/bind works with DEF_MOD. I can however switch to
> > > DEF_MOD_MUX_EXTERNAL for consistency if required.
> > >
> > > Please let me know.
> >
> > Does that mean the monitor bits on RZ/G3E do reflect the correct state of
> > external clocks? If yes, then DEF_MOD() is fine.
> >
> > Gr{oetje,eeting}s,
> >
> > Geert
> >
>
> Checked DEF_MOD() and had expected result. I'll then it and send v3.
>
Can you please share the devmem logs for external clocks please. I ask
because the HW team mentioned the below information will be added in
the RZ/V2H(P) HW manual. We need to check if below is not needed on
RZ/G3E.
"The clock gating cells require source clocks to operate correctly. If
the source clocks are stopped, these registers cannot be used."
Cheers,
Prabhakar
^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [PATCH v2 1/3] clk: renesas: r9a09g047: Add clock and reset signals for the GBETH IPs
2025-06-19 8:21 ` Lad, Prabhakar
@ 2025-06-25 15:18 ` Geert Uytterhoeven
2025-06-30 16:22 ` John Madieu
0 siblings, 1 reply; 19+ messages in thread
From: Geert Uytterhoeven @ 2025-06-25 15:18 UTC (permalink / raw)
To: John Madieu
Cc: andrew+netdev@lunn.ch, conor+dt@kernel.org, davem@davemloft.net,
edumazet@google.com, krzk+dt@kernel.org, kuba@kernel.org,
pabeni@redhat.com, Prabhakar Mahadev Lad, robh@kernel.org,
Biju Das, Lad, Prabhakar, devicetree@vger.kernel.org,
john.madieu@gmail.com, linux-kernel@vger.kernel.org,
linux-renesas-soc@vger.kernel.org, magnus.damm@gmail.com,
netdev@vger.kernel.org
Ho John,
On Thu, 19 Jun 2025 at 10:22, Lad, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> On Thu, Jun 19, 2025 at 5:34 AM John Madieu
> <john.madieu.xa@bp.renesas.com> wrote:
> > > From: Geert Uytterhoeven <geert@linux-m68k.org>
> > > On Wed, 18 Jun 2025 at 12:04, John Madieu <john.madieu.xa@bp.renesas.com>
> > > wrote:
> > > > > From: Geert Uytterhoeven <geert@linux-m68k.org> On Wed, 11 Jun 2025
> > > > > at 11:02, John Madieu <john.madieu.xa@bp.renesas.com>
> > > > > wrote:
> > > > > > Add clock and reset entries for the Gigabit Ethernet Interfaces
> > > > > > (GBETH
> > > > > > 0-1) IPs found on the RZ/G3E SoC. This includes various PLLs,
> > > > > > dividers, and mux clocks needed by these two GBETH IPs.
> > > > > >
> > > > > > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > > > > Tested-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > > > > Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
> > > > >
> > > > > Thanks for your patch!
> > > > >
> > > > > > --- a/drivers/clk/renesas/r9a09g047-cpg.c
> > > > > > +++ b/drivers/clk/renesas/r9a09g047-cpg.c
> > >
> > > > > > @@ -214,6 +252,30 @@ static const struct rzv2h_mod_clk
> > > > > r9a09g047_mod_clks[] __initconst = {
> > > > > > BUS_MSTOP(8,
> > > BIT(4))),
> > > > > > DEF_MOD("sdhi_2_aclk",
> > > CLK_PLLDTY_ACPU_DIV4,
> > > > > 10, 14, 5, 14,
> > > > > > BUS_MSTOP(8,
> > > > > > BIT(4))),
> > > > > > + DEF_MOD("gbeth_0_clk_tx_i",
> > > CLK_SMUX2_GBE0_TXCLK,
> > > > > 11, 8, 5, 24,
> > > > > > + BUS_MSTOP(8,
> > > BIT(5))),
> > > > > > + DEF_MOD("gbeth_0_clk_rx_i",
> > > CLK_SMUX2_GBE0_RXCLK,
> > > > > 11, 9, 5, 25,
> > > > > > + BUS_MSTOP(8,
> > > BIT(5))),
> > > > > > + DEF_MOD("gbeth_0_clk_tx_180_i",
> > > CLK_SMUX2_GBE0_TXCLK,
> > > > > 11, 10, 5, 26,
> > > > > > + BUS_MSTOP(8,
> > > BIT(5))),
> > > > > > + DEF_MOD("gbeth_0_clk_rx_180_i",
> > > CLK_SMUX2_GBE0_RXCLK,
> > > > > 11, 11, 5, 27,
> > > > > > + BUS_MSTOP(8,
> > > BIT(5))),
> > > > > > + DEF_MOD("gbeth_0_aclk_csr_i", CLK_PLLDTY_DIV8, 11,
> > > 12,
> > > > > 5, 28,
> > > > > > + BUS_MSTOP(8,
> > > BIT(5))),
> > > > > > + DEF_MOD("gbeth_0_aclk_i", CLK_PLLDTY_DIV8, 11,
> > > 13,
> > > > > 5, 29,
> > > > > > + BUS_MSTOP(8,
> > > BIT(5))),
> > > > > > + DEF_MOD("gbeth_1_clk_tx_i",
> > > CLK_SMUX2_GBE1_TXCLK,
> > > > > 11, 14, 5, 30,
> > > > > > + BUS_MSTOP(8,
> > > BIT(6))),
> > > > > > + DEF_MOD("gbeth_1_clk_rx_i",
> > > CLK_SMUX2_GBE1_RXCLK,
> > > > > 11, 15, 5, 31,
> > > > > > + BUS_MSTOP(8,
> > > BIT(6))),
> > > > > > + DEF_MOD("gbeth_1_clk_tx_180_i",
> > > CLK_SMUX2_GBE1_TXCLK,
> > > > > 12, 0, 6, 0,
> > > > >
> > > > > scripts/checkpatch.pl says:
> > > > >
> > > > > WARNING: please, no space before tabs
> > > > >
> > > >
> > > > Noted.
> > > >
> > > > > > + BUS_MSTOP(8,
> > > BIT(6))),
> > > > > > + DEF_MOD("gbeth_1_clk_rx_180_i",
> > > CLK_SMUX2_GBE1_RXCLK,
> > > > > 12, 1, 6, 1,
> > > > > > + BUS_MSTOP(8,
> > > BIT(6))),
> > > > > > + DEF_MOD("gbeth_1_aclk_csr_i", CLK_PLLDTY_DIV8, 12,
> > > 2,
> > > > > 6, 2,
> > > > > > + BUS_MSTOP(8,
> > > BIT(6))),
> > > > > > + DEF_MOD("gbeth_1_aclk_i", CLK_PLLDTY_DIV8, 12,
> > > 3,
> > > > > 6, 3,
> > > > > > + BUS_MSTOP(8,
> > > > > > + BIT(6))),
> > > > >
> > > > > Shouldn't all of these use DEF_MOD_MUX_EXTERNAL() instead of
> > > > > DEF_MOD(), like on RZ/V2H and RZ/V2N?
> > > > >
> > > >
> > > > Do we really need to use DEF_MOD_MUX_EXTERNAL? Unlike for the RZ/V2H,
> > > > On G3E, unbind/bind works with DEF_MOD. I can however switch to
> > > > DEF_MOD_MUX_EXTERNAL for consistency if required.
> > > >
> > > > Please let me know.
> > >
> > > Does that mean the monitor bits on RZ/G3E do reflect the correct state of
> > > external clocks? If yes, then DEF_MOD() is fine.
> >
> > Checked DEF_MOD() and had expected result. I'll then it and send v3.
> >
> Can you please share the devmem logs for external clocks please. I ask
> because the HW team mentioned the below information will be added in
> the RZ/V2H(P) HW manual. We need to check if below is not needed on
> RZ/G3E.
>
> "The clock gating cells require source clocks to operate correctly. If
> the source clocks are stopped, these registers cannot be used."
Has this been sorted out yet? I see no change or mention of it in v3.
Thanks!
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 19+ messages in thread* RE: [PATCH v2 1/3] clk: renesas: r9a09g047: Add clock and reset signals for the GBETH IPs
2025-06-25 15:18 ` Geert Uytterhoeven
@ 2025-06-30 16:22 ` John Madieu
2025-07-01 8:05 ` Geert Uytterhoeven
0 siblings, 1 reply; 19+ messages in thread
From: John Madieu @ 2025-06-30 16:22 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: andrew+netdev@lunn.ch, conor+dt@kernel.org, davem@davemloft.net,
edumazet@google.com, krzk+dt@kernel.org, kuba@kernel.org,
pabeni@redhat.com, Prabhakar Mahadev Lad, robh@kernel.org,
Biju Das, Lad, Prabhakar, devicetree@vger.kernel.org,
john.madieu@gmail.com, linux-kernel@vger.kernel.org,
linux-renesas-soc@vger.kernel.org, magnus.damm@gmail.com,
netdev@vger.kernel.org
Hi Geert,
> -----Original Message-----
> From: Geert Uytterhoeven <geert@linux-m68k.org>
> Sent: Wednesday, June 25, 2025 5:19 PM
> To: John Madieu <john.madieu.xa@bp.renesas.com>
> Subject: Re: [PATCH v2 1/3] clk: renesas: r9a09g047: Add clock and reset
> signals for the GBETH IPs
>
> Ho John,
>
> On Thu, 19 Jun 2025 at 10:22, Lad, Prabhakar <prabhakar.csengg@gmail.com>
> wrote:
> > On Thu, Jun 19, 2025 at 5:34 AM John Madieu
> > <john.madieu.xa@bp.renesas.com> wrote:
> > > > From: Geert Uytterhoeven <geert@linux-m68k.org> On Wed, 18 Jun
> > > > 2025 at 12:04, John Madieu <john.madieu.xa@bp.renesas.com>
> > > > wrote:
> > > > > > From: Geert Uytterhoeven <geert@linux-m68k.org> On Wed, 11 Jun
> > > > > > 2025 at 11:02, John Madieu <john.madieu.xa@bp.renesas.com>
> > > > > > wrote:
> > > > > > > Add clock and reset entries for the Gigabit Ethernet
> > > > > > > Interfaces (GBETH
> > > > > > > 0-1) IPs found on the RZ/G3E SoC. This includes various
> > > > > > > PLLs, dividers, and mux clocks needed by these two GBETH IPs.
> > > > > > >
> > > > > > > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > > > > > Tested-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > > > > > Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
> > > > > >
> > > > > > Thanks for your patch!
> > > > > >
> > > > > > > --- a/drivers/clk/renesas/r9a09g047-cpg.c
> > > > > > > +++ b/drivers/clk/renesas/r9a09g047-cpg.c
> > > >
> >
> > "The clock gating cells require source clocks to operate correctly. If
> > the source clocks are stopped, these registers cannot be used."
>
> Has this been sorted out yet? I see no change or mention of it in v3.
>
Yes, it has been sorted out. I mean they operated properly after
all the tests, even after S2R/wakeup test.
While at it, even with OEN patches applied, I could not reproduce
the issue known to V2H. That's why I've asked if you'd prefer
DEF_MOD_EXTERNAL instead of DEF_MOD (which does not work on V2H)
for consistency with RZ/V2H, I can do that as well.
>
> Gr{oetje,eeting}s,
>
> Geert
>
Regards,
John
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-
> m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like
> that.
> -- Linus Torvalds
^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [PATCH v2 1/3] clk: renesas: r9a09g047: Add clock and reset signals for the GBETH IPs
2025-06-30 16:22 ` John Madieu
@ 2025-07-01 8:05 ` Geert Uytterhoeven
0 siblings, 0 replies; 19+ messages in thread
From: Geert Uytterhoeven @ 2025-07-01 8:05 UTC (permalink / raw)
To: John Madieu
Cc: andrew+netdev@lunn.ch, conor+dt@kernel.org, davem@davemloft.net,
edumazet@google.com, krzk+dt@kernel.org, kuba@kernel.org,
pabeni@redhat.com, Prabhakar Mahadev Lad, robh@kernel.org,
Biju Das, Lad, Prabhakar, devicetree@vger.kernel.org,
john.madieu@gmail.com, linux-kernel@vger.kernel.org,
linux-renesas-soc@vger.kernel.org, magnus.damm@gmail.com,
netdev@vger.kernel.org
Hi John,
On Mon, 30 Jun 2025 at 18:23, John Madieu <john.madieu.xa@bp.renesas.com> wrote:
> > From: Geert Uytterhoeven <geert@linux-m68k.org>
> > On Thu, 19 Jun 2025 at 10:22, Lad, Prabhakar <prabhakar.csengg@gmail.com>
> > wrote:
> > > On Thu, Jun 19, 2025 at 5:34 AM John Madieu
> > > <john.madieu.xa@bp.renesas.com> wrote:
> > > > > From: Geert Uytterhoeven <geert@linux-m68k.org> On Wed, 18 Jun
> > > > > 2025 at 12:04, John Madieu <john.madieu.xa@bp.renesas.com>
> > > > > wrote:
> > > > > > > From: Geert Uytterhoeven <geert@linux-m68k.org> On Wed, 11 Jun
> > > > > > > 2025 at 11:02, John Madieu <john.madieu.xa@bp.renesas.com>
> > > > > > > wrote:
> > > > > > > > Add clock and reset entries for the Gigabit Ethernet
> > > > > > > > Interfaces (GBETH
> > > > > > > > 0-1) IPs found on the RZ/G3E SoC. This includes various
> > > > > > > > PLLs, dividers, and mux clocks needed by these two GBETH IPs.
> > > > > > > >
> > > > > > > > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > > > > > > Tested-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > > > > > > Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
> > > > > > >
> > > > > > > Thanks for your patch!
> > > > > > >
> > > > > > > > --- a/drivers/clk/renesas/r9a09g047-cpg.c
> > > > > > > > +++ b/drivers/clk/renesas/r9a09g047-cpg.c
> > >
> > > "The clock gating cells require source clocks to operate correctly. If
> > > the source clocks are stopped, these registers cannot be used."
> >
> > Has this been sorted out yet? I see no change or mention of it in v3.
>
> Yes, it has been sorted out. I mean they operated properly after
> all the tests, even after S2R/wakeup test.
>
> While at it, even with OEN patches applied, I could not reproduce
> the issue known to V2H. That's why I've asked if you'd prefer
> DEF_MOD_EXTERNAL instead of DEF_MOD (which does not work on V2H)
> for consistency with RZ/V2H, I can do that as well.
As DEF_MOD_MUX_EXTERNAL() better matches the undelying
hardware, I prefer that.
Thanks!
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v2 2/3] arm64: dts: renesas: r9a09g047: Add GBETH nodes
2025-06-11 6:16 [PATCH v2 0/3] Add support for GBETH IPs found on RZ/G3E SoCs John Madieu
2025-06-11 6:16 ` [PATCH v2 1/3] clk: renesas: r9a09g047: Add clock and reset signals for the GBETH IPs John Madieu
@ 2025-06-11 6:16 ` John Madieu
2025-06-17 15:32 ` Geert Uytterhoeven
2025-06-11 6:16 ` [PATCH v2 3/3] arm64: dts: renesas: rzg3e-smarc-som: Enable eth{0-1} (GBETH) interfaces John Madieu
2025-06-12 20:12 ` [PATCH v2 0/3] Add support for GBETH IPs found on RZ/G3E SoCs Rob Herring (Arm)
3 siblings, 1 reply; 19+ messages in thread
From: John Madieu @ 2025-06-11 6:16 UTC (permalink / raw)
To: andrew+netdev, conor+dt, davem, edumazet, geert+renesas, krzk+dt,
kuba, pabeni, prabhakar.mahadev-lad.rj, robh
Cc: biju.das.jz, devicetree, john.madieu, linux-kernel,
linux-renesas-soc, magnus.damm, netdev, John Madieu
Add GBETH nodes to RZ/G3E (R9A09G047) SoC DTSI.
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Tested-by: Biju Das <biju.das.jz@bp.renesas.com>
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 207 +++++++++++++++++++++
1 file changed, 207 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
index a0d4fab4fe05..e6e35b41a9d3 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
@@ -759,6 +759,213 @@ csi2cru: endpoint@0 {
};
};
};
+
+ eth0: ethernet@15c30000 {
+ compatible = "renesas,r9a09g047-gbeth", "renesas,rzv2h-gbeth", "snps,dwmac-5.20";
+ reg = <0 0x15c30000 0 0x10000>;
+ clocks = <&cpg CPG_MOD 0xbd>, <&cpg CPG_MOD 0xbc>,
+ <&cpg CPG_CORE R9A09G047_GBETH_0_CLK_PTP_REF_I>,
+ <&cpg CPG_MOD 0xb8>, <&cpg CPG_MOD 0xb9>,
+ <&cpg CPG_MOD 0xba>, <&cpg CPG_MOD 0xbb>;
+ clock-names = "stmmaceth", "pclk", "ptp_ref",
+ "tx", "rx", "tx-180", "rx-180";
+ interrupts = <GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 767 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 775 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq", "eth_wake_irq", "eth_lpi",
+ "rx-queue-0", "rx-queue-1", "rx-queue-2",
+ "rx-queue-3", "tx-queue-0", "tx-queue-1",
+ "tx-queue-2", "tx-queue-3";
+ resets = <&cpg 0xb0>;
+ power-domains = <&cpg>;
+ snps,multicast-filter-bins = <256>;
+ snps,perfect-filter-entries = <128>;
+ rx-fifo-depth = <8192>;
+ tx-fifo-depth = <8192>;
+ snps,fixed-burst;
+ snps,no-pbl-x8;
+ snps,force_thresh_dma_mode;
+ snps,axi-config = <&stmmac_axi_setup>;
+ snps,mtl-rx-config = <&mtl_rx_setup0>;
+ snps,mtl-tx-config = <&mtl_tx_setup0>;
+ snps,txpbl = <32>;
+ snps,rxpbl = <32>;
+ status = "disabled";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mtl_rx_setup0: rx-queues-config {
+ snps,rx-queues-to-use = <4>;
+ snps,rx-sched-sp;
+
+ queue0 {
+ snps,dcb-algorithm;
+ snps,priority = <0x1>;
+ snps,map-to-dma-channel = <0>;
+ };
+
+ queue1 {
+ snps,dcb-algorithm;
+ snps,priority = <0x2>;
+ snps,map-to-dma-channel = <1>;
+ };
+
+ queue2 {
+ snps,dcb-algorithm;
+ snps,priority = <0x4>;
+ snps,map-to-dma-channel = <2>;
+ };
+
+ queue3 {
+ snps,dcb-algorithm;
+ snps,priority = <0x8>;
+ snps,map-to-dma-channel = <3>;
+ };
+ };
+
+ mtl_tx_setup0: tx-queues-config {
+ snps,tx-queues-to-use = <4>;
+
+ queue0 {
+ snps,dcb-algorithm;
+ snps,priority = <0x1>;
+ };
+
+ queue1 {
+ snps,dcb-algorithm;
+ snps,priority = <0x2>;
+ };
+
+ queue2 {
+ snps,dcb-algorithm;
+ snps,priority = <0x4>;
+ };
+
+ queue3 {
+ snps,dcb-algorithm;
+ snps,priority = <0x8>;
+ };
+ };
+ };
+
+ eth1: ethernet@15c40000 {
+ compatible = "renesas,r9a09g047-gbeth", "renesas,rzv2h-gbeth", "snps,dwmac-5.20";
+ reg = <0 0x15c40000 0 0x10000>;
+ clocks = <&cpg CPG_MOD 0xc3>, <&cpg CPG_MOD 0xc2>,
+ <&cpg CPG_CORE R9A09G047_GBETH_1_CLK_PTP_REF_I>,
+ <&cpg CPG_MOD 0xbe>, <&cpg CPG_MOD 0xbf>,
+ <&cpg CPG_MOD 0xc0>, <&cpg CPG_MOD 0xc1>;
+ clock-names = "stmmaceth", "pclk", "ptp_ref",
+ "tx", "rx", "tx-180", "rx-180";
+ interrupts = <GIC_SPI 780 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 789 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 786 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq", "eth_wake_irq", "eth_lpi",
+ "rx-queue-0", "rx-queue-1", "rx-queue-2",
+ "rx-queue-3", "tx-queue-0", "tx-queue-1",
+ "tx-queue-2", "tx-queue-3";
+ resets = <&cpg 0xb1>;
+ power-domains = <&cpg>;
+ snps,multicast-filter-bins = <256>;
+ snps,perfect-filter-entries = <128>;
+ rx-fifo-depth = <8192>;
+ tx-fifo-depth = <8192>;
+ snps,fixed-burst;
+ snps,no-pbl-x8;
+ snps,force_thresh_dma_mode;
+ snps,axi-config = <&stmmac_axi_setup>;
+ snps,mtl-rx-config = <&mtl_rx_setup1>;
+ snps,mtl-tx-config = <&mtl_tx_setup1>;
+ snps,txpbl = <32>;
+ snps,rxpbl = <32>;
+ status = "disabled";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mtl_rx_setup1: rx-queues-config {
+ snps,rx-queues-to-use = <4>;
+ snps,rx-sched-sp;
+
+ queue0 {
+ snps,dcb-algorithm;
+ snps,priority = <0x1>;
+ snps,map-to-dma-channel = <0>;
+ };
+
+ queue1 {
+ snps,dcb-algorithm;
+ snps,priority = <0x2>;
+ snps,map-to-dma-channel = <1>;
+ };
+
+ queue2 {
+ snps,dcb-algorithm;
+ snps,priority = <0x4>;
+ snps,map-to-dma-channel = <2>;
+ };
+
+ queue3 {
+ snps,dcb-algorithm;
+ snps,priority = <0x8>;
+ snps,map-to-dma-channel = <3>;
+ };
+ };
+
+ mtl_tx_setup1: tx-queues-config {
+ snps,tx-queues-to-use = <4>;
+
+ queue0 {
+ snps,dcb-algorithm;
+ snps,priority = <0x1>;
+ };
+
+ queue1 {
+ snps,dcb-algorithm;
+ snps,priority = <0x2>;
+ };
+
+ queue2 {
+ snps,dcb-algorithm;
+ snps,priority = <0x4>;
+ };
+
+ queue3 {
+ snps,dcb-algorithm;
+ snps,priority = <0x8>;
+ };
+ };
+ };
+ };
+
+ stmmac_axi_setup: stmmac-axi-config {
+ snps,lpi_en;
+ snps,wr_osr_lmt = <0xf>;
+ snps,rd_osr_lmt = <0xf>;
+ snps,blen = <16 8 4 0 0 0 0>;
};
timer {
--
2.25.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [PATCH v2 2/3] arm64: dts: renesas: r9a09g047: Add GBETH nodes
2025-06-11 6:16 ` [PATCH v2 2/3] arm64: dts: renesas: r9a09g047: Add GBETH nodes John Madieu
@ 2025-06-17 15:32 ` Geert Uytterhoeven
2025-06-18 8:54 ` John Madieu
0 siblings, 1 reply; 19+ messages in thread
From: Geert Uytterhoeven @ 2025-06-17 15:32 UTC (permalink / raw)
To: John Madieu
Cc: andrew+netdev, conor+dt, davem, edumazet, krzk+dt, kuba, pabeni,
prabhakar.mahadev-lad.rj, robh, biju.das.jz, devicetree,
john.madieu, linux-kernel, linux-renesas-soc, magnus.damm, netdev
Hi John,
On Wed, 11 Jun 2025 at 11:01, John Madieu <john.madieu.xa@bp.renesas.com> wrote:
> Add GBETH nodes to RZ/G3E (R9A09G047) SoC DTSI.
>
> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> Tested-by: Biju Das <biju.das.jz@bp.renesas.com>
> Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
Thanks for your patch!
> --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
> @@ -759,6 +759,213 @@ csi2cru: endpoint@0 {
> };
> };
> };
> +
> + eth0: ethernet@15c30000 {
[...]
> + mdio {
You probably want to add a label (mdio0) here...
> + compatible = "snps,dwmac-mdio";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + eth1: ethernet@15c40000 {
[...]
> + mdio {
... and here (mdio1), for easier configuration of the PHY in the
board-specific DTS.
> + compatible = "snps,dwmac-mdio";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
The rest LGTM, so
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 19+ messages in thread* RE: [PATCH v2 2/3] arm64: dts: renesas: r9a09g047: Add GBETH nodes
2025-06-17 15:32 ` Geert Uytterhoeven
@ 2025-06-18 8:54 ` John Madieu
0 siblings, 0 replies; 19+ messages in thread
From: John Madieu @ 2025-06-18 8:54 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: andrew+netdev@lunn.ch, conor+dt@kernel.org, davem@davemloft.net,
edumazet@google.com, krzk+dt@kernel.org, kuba@kernel.org,
pabeni@redhat.com, Prabhakar Mahadev Lad, robh@kernel.org,
Biju Das, devicetree@vger.kernel.org, john.madieu@gmail.com,
linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
magnus.damm@gmail.com, netdev@vger.kernel.org
Hi Geert,
Thanks for your review.
> -----Original Message-----
> From: Geert Uytterhoeven <geert@linux-m68k.org>
> Sent: Tuesday, June 17, 2025 5:32 PM
> To: John Madieu <john.madieu.xa@bp.renesas.com>
> Subject: Re: [PATCH v2 2/3] arm64: dts: renesas: r9a09g047: Add GBETH
> nodes
>
> Hi John,
>
> On Wed, 11 Jun 2025 at 11:01, John Madieu <john.madieu.xa@bp.renesas.com>
> wrote:
> > Add GBETH nodes to RZ/G3E (R9A09G047) SoC DTSI.
> >
> > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> > Tested-by: Biju Das <biju.das.jz@bp.renesas.com>
> > Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
>
> Thanks for your patch!
>
> > --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
> > @@ -759,6 +759,213 @@ csi2cru: endpoint@0 {
> > };
> > };
> > };
> > +
> > + eth0: ethernet@15c30000 {
>
> [...]
>
> > + mdio {
>
> You probably want to add a label (mdio0) here...
>
Noted.
> > + compatible = "snps,dwmac-mdio";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + };
>
> > + eth1: ethernet@15c40000 {
>
> [...]
>
> > + mdio {
>
> ... and here (mdio1), for easier configuration of the PHY in the board-
> specific DTS.
>
Noted.
Will address that in v3.
> > + compatible = "snps,dwmac-mdio";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + };
>
> The rest LGTM, so
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>
> Gr{oetje,eeting}s,
>
> Geert
>
Regards,
John
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-
> m68k.org
>
> In personal conversations with technical people, I call myself a hacker.
> But when I'm talking to journalists I just say "programmer" or something
> like that.
> -- Linus Torvalds
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v2 3/3] arm64: dts: renesas: rzg3e-smarc-som: Enable eth{0-1} (GBETH) interfaces
2025-06-11 6:16 [PATCH v2 0/3] Add support for GBETH IPs found on RZ/G3E SoCs John Madieu
2025-06-11 6:16 ` [PATCH v2 1/3] clk: renesas: r9a09g047: Add clock and reset signals for the GBETH IPs John Madieu
2025-06-11 6:16 ` [PATCH v2 2/3] arm64: dts: renesas: r9a09g047: Add GBETH nodes John Madieu
@ 2025-06-11 6:16 ` John Madieu
2025-06-17 15:50 ` Geert Uytterhoeven
2025-06-19 8:59 ` Lad, Prabhakar
2025-06-12 20:12 ` [PATCH v2 0/3] Add support for GBETH IPs found on RZ/G3E SoCs Rob Herring (Arm)
3 siblings, 2 replies; 19+ messages in thread
From: John Madieu @ 2025-06-11 6:16 UTC (permalink / raw)
To: andrew+netdev, conor+dt, davem, edumazet, geert+renesas, krzk+dt,
kuba, pabeni, prabhakar.mahadev-lad.rj, robh
Cc: biju.das.jz, devicetree, john.madieu, linux-kernel,
linux-renesas-soc, magnus.damm, netdev, John Madieu
Enable the Gigabit Ethernet Interfaces (GBETH) populated on the RZ/G3E SMARC EVK
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Tested-by: Biju Das <biju.das.jz@bp.renesas.com>
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---
.../boot/dts/renesas/rzg3e-smarc-som.dtsi | 106 ++++++++++++++++++
1 file changed, 106 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
index f99a09d04ddd..4b4c7f3381ad 100644
--- a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
@@ -26,6 +26,8 @@ / {
compatible = "renesas,rzg3e-smarcm", "renesas,r9a09g047e57", "renesas,r9a09g047";
aliases {
+ ethernet0 = ð0;
+ ethernet1 = ð1;
i2c2 = &i2c2;
mmc0 = &sdhi0;
mmc2 = &sdhi2;
@@ -77,6 +79,74 @@ &audio_extal_clk {
clock-frequency = <48000000>;
};
+ð0 {
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+
+ pinctrl-0 = <ð0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+
+ phy0: ethernet-phy@7 {
+ compatible = "ethernet-phy-id0022.1640",
+ "ethernet-phy-ieee802.3-c22";
+ reg = <7>;
+ interrupts-extended = <&icu 3 IRQ_TYPE_LEVEL_LOW>;
+ rxc-skew-psec = <1400>;
+ txc-skew-psec = <1400>;
+ rxdv-skew-psec = <0>;
+ txdv-skew-psec = <0>;
+ rxd0-skew-psec = <0>;
+ rxd1-skew-psec = <0>;
+ rxd2-skew-psec = <0>;
+ rxd3-skew-psec = <0>;
+ txd0-skew-psec = <0>;
+ txd1-skew-psec = <0>;
+ txd2-skew-psec = <0>;
+ txd3-skew-psec = <0>;
+ };
+ };
+};
+
+ð1 {
+ phy-handle = <&phy1>;
+ phy-mode = "rgmii-id";
+
+ pinctrl-0 = <ð1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+
+ phy1: ethernet-phy@7 {
+ compatible = "ethernet-phy-id0022.1640",
+ "ethernet-phy-ieee802.3-c22";
+ reg = <7>;
+ interrupts-extended = <&icu 16 IRQ_TYPE_LEVEL_LOW>;
+ rxc-skew-psec = <1400>;
+ txc-skew-psec = <1400>;
+ rxdv-skew-psec = <0>;
+ txdv-skew-psec = <0>;
+ rxd0-skew-psec = <0>;
+ rxd1-skew-psec = <0>;
+ rxd2-skew-psec = <0>;
+ rxd3-skew-psec = <0>;
+ txd0-skew-psec = <0>;
+ txd1-skew-psec = <0>;
+ txd2-skew-psec = <0>;
+ txd3-skew-psec = <0>;
+ };
+ };
+};
+
&gpu {
status = "okay";
mali-supply = <®_vdd0p8v_others>;
@@ -103,6 +173,42 @@ raa215300: pmic@12 {
};
&pinctrl {
+ eth0_pins: eth0 {
+ pinmux = <RZG3E_PORT_PINMUX(A, 1, 1)>, /* MDC */
+ <RZG3E_PORT_PINMUX(A, 0, 1)>, /* MDIO */
+ <RZG3E_PORT_PINMUX(C, 2, 15)>, /* PHY_INTR (IRQ2) */
+ <RZG3E_PORT_PINMUX(C, 1, 1)>, /* RXD3 */
+ <RZG3E_PORT_PINMUX(C, 0, 1)>, /* RXD2 */
+ <RZG3E_PORT_PINMUX(B, 7, 1)>, /* RXD1 */
+ <RZG3E_PORT_PINMUX(B, 6, 1)>, /* RXD0 */
+ <RZG3E_PORT_PINMUX(B, 0, 1)>, /* RXC */
+ <RZG3E_PORT_PINMUX(A, 2, 1)>, /* RX_CTL */
+ <RZG3E_PORT_PINMUX(B, 5, 1)>, /* TXD3 */
+ <RZG3E_PORT_PINMUX(B, 4, 1)>, /* TXD2 */
+ <RZG3E_PORT_PINMUX(B, 3, 1)>, /* TXD1 */
+ <RZG3E_PORT_PINMUX(B, 2, 1)>, /* TXD0 */
+ <RZG3E_PORT_PINMUX(B, 1, 1)>, /* TXC */
+ <RZG3E_PORT_PINMUX(A, 3, 1)>; /* TX_CTL */
+ };
+
+ eth1_pins: eth1 {
+ pinmux = <RZG3E_PORT_PINMUX(D, 1, 1)>, /* MDC */
+ <RZG3E_PORT_PINMUX(D, 0, 1)>, /* MDIO */
+ <RZG3E_PORT_PINMUX(F, 2, 15)>, /* PHY_INTR (IRQ15) */
+ <RZG3E_PORT_PINMUX(F, 1, 1)>, /* RXD3 */
+ <RZG3E_PORT_PINMUX(F, 0, 1)>, /* RXD2 */
+ <RZG3E_PORT_PINMUX(E, 7, 1)>, /* RXD1 */
+ <RZG3E_PORT_PINMUX(E, 6, 1)>, /* RXD0 */
+ <RZG3E_PORT_PINMUX(E, 0, 1)>, /* RXC */
+ <RZG3E_PORT_PINMUX(D, 2, 1)>, /* RX_CTL */
+ <RZG3E_PORT_PINMUX(E, 5, 1)>, /* TXD3 */
+ <RZG3E_PORT_PINMUX(E, 4, 1)>, /* TXD2 */
+ <RZG3E_PORT_PINMUX(E, 3, 1)>, /* TXD1 */
+ <RZG3E_PORT_PINMUX(E, 2, 1)>, /* TXD0 */
+ <RZG3E_PORT_PINMUX(E, 1, 1)>, /* TXC */
+ <RZG3E_PORT_PINMUX(D, 3, 1)>; /* TX_CTL */
+ };
+
i2c2_pins: i2c {
pinmux = <RZG3E_PORT_PINMUX(3, 4, 1)>, /* SCL2 */
<RZG3E_PORT_PINMUX(3, 5, 1)>; /* SDA2 */
--
2.25.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [PATCH v2 3/3] arm64: dts: renesas: rzg3e-smarc-som: Enable eth{0-1} (GBETH) interfaces
2025-06-11 6:16 ` [PATCH v2 3/3] arm64: dts: renesas: rzg3e-smarc-som: Enable eth{0-1} (GBETH) interfaces John Madieu
@ 2025-06-17 15:50 ` Geert Uytterhoeven
2025-06-18 8:47 ` John Madieu
2025-06-19 8:59 ` Lad, Prabhakar
1 sibling, 1 reply; 19+ messages in thread
From: Geert Uytterhoeven @ 2025-06-17 15:50 UTC (permalink / raw)
To: John Madieu
Cc: andrew+netdev, conor+dt, davem, edumazet, krzk+dt, kuba, pabeni,
prabhakar.mahadev-lad.rj, robh, biju.das.jz, devicetree,
john.madieu, linux-kernel, linux-renesas-soc, magnus.damm, netdev
Hi John,
On Wed, 11 Jun 2025 at 11:00, John Madieu <john.madieu.xa@bp.renesas.com> wrote:
> Enable the Gigabit Ethernet Interfaces (GBETH) populated on the RZ/G3E SMARC EVK
>
> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> Tested-by: Biju Das <biju.das.jz@bp.renesas.com>
> Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
Thanks for your patch!
> --- a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
> +++ b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
> @@ -77,6 +79,74 @@ &audio_extal_clk {
> clock-frequency = <48000000>;
> };
>
> +ð0 {
> + phy-handle = <&phy0>;
> + phy-mode = "rgmii-id";
> +
> + pinctrl-0 = <ð0_pins>;
> + pinctrl-names = "default";
> + status = "okay";
> +
> + mdio {
&mdio0 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "snps,dwmac-mdio";
No need for these three properties, as they are already present in the
SoC-specific DTS with the exact same values.
Same for the second interface.
The rest LGTM, so with the above fixed:
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 19+ messages in thread* RE: [PATCH v2 3/3] arm64: dts: renesas: rzg3e-smarc-som: Enable eth{0-1} (GBETH) interfaces
2025-06-17 15:50 ` Geert Uytterhoeven
@ 2025-06-18 8:47 ` John Madieu
0 siblings, 0 replies; 19+ messages in thread
From: John Madieu @ 2025-06-18 8:47 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: andrew+netdev@lunn.ch, conor+dt@kernel.org, davem@davemloft.net,
edumazet@google.com, krzk+dt@kernel.org, kuba@kernel.org,
pabeni@redhat.com, Prabhakar Mahadev Lad, robh@kernel.org,
Biju Das, devicetree@vger.kernel.org, john.madieu@gmail.com,
linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
magnus.damm@gmail.com, netdev@vger.kernel.org
Hello Geert,
Thanks for your review.
> -----Original Message-----
> From: Geert Uytterhoeven <geert@linux-m68k.org>
> Sent: Tuesday, June 17, 2025 5:51 PM
> To: John Madieu <john.madieu.xa@bp.renesas.com>
> Subject: Re: [PATCH v2 3/3] arm64: dts: renesas: rzg3e-smarc-som: Enable
> eth{0-1} (GBETH) interfaces
>
> Hi John,
>
> On Wed, 11 Jun 2025 at 11:00, John Madieu <john.madieu.xa@bp.renesas.com>
> wrote:
> > Enable the Gigabit Ethernet Interfaces (GBETH) populated on the RZ/G3E
> > SMARC EVK
> >
> > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> > Tested-by: Biju Das <biju.das.jz@bp.renesas.com>
> > Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
>
> Thanks for your patch!
>
> > --- a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
>
> > @@ -77,6 +79,74 @@ &audio_extal_clk {
> > clock-frequency = <48000000>;
> > };
> >
> > +ð0 {
> > + phy-handle = <&phy0>;
> > + phy-mode = "rgmii-id";
> > +
> > + pinctrl-0 = <ð0_pins>;
> > + pinctrl-names = "default";
> > + status = "okay";
> > +
> > + mdio {
>
> &mdio0 {
>
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + compatible = "snps,dwmac-mdio";
>
> No need for these three properties, as they are already present in the
> SoC-specific DTS with the exact same values.
>
> Same for the second interface.
Noted. Will handle that in the v3.
>
> The rest LGTM, so with the above fixed:
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>
> Gr{oetje,eeting}s,
>
> Geert
>
Regards,
John
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-
> m68k.org
>
> In personal conversations with technical people, I call myself a hacker.
> But when I'm talking to journalists I just say "programmer" or something
> like that.
> -- Linus Torvalds
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v2 3/3] arm64: dts: renesas: rzg3e-smarc-som: Enable eth{0-1} (GBETH) interfaces
2025-06-11 6:16 ` [PATCH v2 3/3] arm64: dts: renesas: rzg3e-smarc-som: Enable eth{0-1} (GBETH) interfaces John Madieu
2025-06-17 15:50 ` Geert Uytterhoeven
@ 2025-06-19 8:59 ` Lad, Prabhakar
2025-06-19 11:09 ` John Madieu
1 sibling, 1 reply; 19+ messages in thread
From: Lad, Prabhakar @ 2025-06-19 8:59 UTC (permalink / raw)
To: John Madieu
Cc: andrew+netdev, conor+dt, davem, edumazet, geert+renesas, krzk+dt,
kuba, pabeni, prabhakar.mahadev-lad.rj, robh, biju.das.jz,
devicetree, john.madieu, linux-kernel, linux-renesas-soc,
magnus.damm, netdev
Hi John,
Thank you for the patch.
On Wed, Jun 11, 2025 at 7:20 AM John Madieu
<john.madieu.xa@bp.renesas.com> wrote:
>
> Enable the Gigabit Ethernet Interfaces (GBETH) populated on the RZ/G3E SMARC EVK
>
> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> Tested-by: Biju Das <biju.das.jz@bp.renesas.com>
> Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
> ---
> .../boot/dts/renesas/rzg3e-smarc-som.dtsi | 106 ++++++++++++++++++
> 1 file changed, 106 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
> index f99a09d04ddd..4b4c7f3381ad 100644
> --- a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
> +++ b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
> @@ -26,6 +26,8 @@ / {
> compatible = "renesas,rzg3e-smarcm", "renesas,r9a09g047e57", "renesas,r9a09g047";
>
> aliases {
> + ethernet0 = ð0;
> + ethernet1 = ð1;
> i2c2 = &i2c2;
> mmc0 = &sdhi0;
> mmc2 = &sdhi2;
> @@ -77,6 +79,74 @@ &audio_extal_clk {
> clock-frequency = <48000000>;
> };
>
> +ð0 {
> + phy-handle = <&phy0>;
> + phy-mode = "rgmii-id";
> +
> + pinctrl-0 = <ð0_pins>;
> + pinctrl-names = "default";
> + status = "okay";
> +
> + mdio {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "snps,dwmac-mdio";
> +
> + phy0: ethernet-phy@7 {
> + compatible = "ethernet-phy-id0022.1640",
> + "ethernet-phy-ieee802.3-c22";
> + reg = <7>;
> + interrupts-extended = <&icu 3 IRQ_TYPE_LEVEL_LOW>;
> + rxc-skew-psec = <1400>;
> + txc-skew-psec = <1400>;
> + rxdv-skew-psec = <0>;
> + txdv-skew-psec = <0>;
> + rxd0-skew-psec = <0>;
> + rxd1-skew-psec = <0>;
> + rxd2-skew-psec = <0>;
> + rxd3-skew-psec = <0>;
> + txd0-skew-psec = <0>;
> + txd1-skew-psec = <0>;
> + txd2-skew-psec = <0>;
> + txd3-skew-psec = <0>;
> + };
> + };
> +};
> +
> +ð1 {
> + phy-handle = <&phy1>;
> + phy-mode = "rgmii-id";
> +
> + pinctrl-0 = <ð1_pins>;
> + pinctrl-names = "default";
> + status = "okay";
> +
> + mdio {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "snps,dwmac-mdio";
> +
> + phy1: ethernet-phy@7 {
> + compatible = "ethernet-phy-id0022.1640",
> + "ethernet-phy-ieee802.3-c22";
> + reg = <7>;
> + interrupts-extended = <&icu 16 IRQ_TYPE_LEVEL_LOW>;
> + rxc-skew-psec = <1400>;
> + txc-skew-psec = <1400>;
> + rxdv-skew-psec = <0>;
> + txdv-skew-psec = <0>;
> + rxd0-skew-psec = <0>;
> + rxd1-skew-psec = <0>;
> + rxd2-skew-psec = <0>;
> + rxd3-skew-psec = <0>;
> + txd0-skew-psec = <0>;
> + txd1-skew-psec = <0>;
> + txd2-skew-psec = <0>;
> + txd3-skew-psec = <0>;
> + };
> + };
> +};
> +
> &gpu {
> status = "okay";
> mali-supply = <®_vdd0p8v_others>;
> @@ -103,6 +173,42 @@ raa215300: pmic@12 {
> };
>
> &pinctrl {
> + eth0_pins: eth0 {
> + pinmux = <RZG3E_PORT_PINMUX(A, 1, 1)>, /* MDC */
> + <RZG3E_PORT_PINMUX(A, 0, 1)>, /* MDIO */
> + <RZG3E_PORT_PINMUX(C, 2, 15)>, /* PHY_INTR (IRQ2) */
> + <RZG3E_PORT_PINMUX(C, 1, 1)>, /* RXD3 */
> + <RZG3E_PORT_PINMUX(C, 0, 1)>, /* RXD2 */
> + <RZG3E_PORT_PINMUX(B, 7, 1)>, /* RXD1 */
> + <RZG3E_PORT_PINMUX(B, 6, 1)>, /* RXD0 */
> + <RZG3E_PORT_PINMUX(B, 0, 1)>, /* RXC */
> + <RZG3E_PORT_PINMUX(A, 2, 1)>, /* RX_CTL */
> + <RZG3E_PORT_PINMUX(B, 5, 1)>, /* TXD3 */
> + <RZG3E_PORT_PINMUX(B, 4, 1)>, /* TXD2 */
> + <RZG3E_PORT_PINMUX(B, 3, 1)>, /* TXD1 */
> + <RZG3E_PORT_PINMUX(B, 2, 1)>, /* TXD0 */
> + <RZG3E_PORT_PINMUX(B, 1, 1)>, /* TXC */
> + <RZG3E_PORT_PINMUX(A, 3, 1)>; /* TX_CTL */
like RZ/V2H on RZ/G3E PFC_OEN BITS(0,1) need to be configured based on
RGMII/MII mode?
Cheers,
Prabhakar
> + };
> +
> + eth1_pins: eth1 {
> + pinmux = <RZG3E_PORT_PINMUX(D, 1, 1)>, /* MDC */
> + <RZG3E_PORT_PINMUX(D, 0, 1)>, /* MDIO */
> + <RZG3E_PORT_PINMUX(F, 2, 15)>, /* PHY_INTR (IRQ15) */
> + <RZG3E_PORT_PINMUX(F, 1, 1)>, /* RXD3 */
> + <RZG3E_PORT_PINMUX(F, 0, 1)>, /* RXD2 */
> + <RZG3E_PORT_PINMUX(E, 7, 1)>, /* RXD1 */
> + <RZG3E_PORT_PINMUX(E, 6, 1)>, /* RXD0 */
> + <RZG3E_PORT_PINMUX(E, 0, 1)>, /* RXC */
> + <RZG3E_PORT_PINMUX(D, 2, 1)>, /* RX_CTL */
> + <RZG3E_PORT_PINMUX(E, 5, 1)>, /* TXD3 */
> + <RZG3E_PORT_PINMUX(E, 4, 1)>, /* TXD2 */
> + <RZG3E_PORT_PINMUX(E, 3, 1)>, /* TXD1 */
> + <RZG3E_PORT_PINMUX(E, 2, 1)>, /* TXD0 */
> + <RZG3E_PORT_PINMUX(E, 1, 1)>, /* TXC */
> + <RZG3E_PORT_PINMUX(D, 3, 1)>; /* TX_CTL */
> + };
> +
> i2c2_pins: i2c {
> pinmux = <RZG3E_PORT_PINMUX(3, 4, 1)>, /* SCL2 */
> <RZG3E_PORT_PINMUX(3, 5, 1)>; /* SDA2 */
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 19+ messages in thread* RE: [PATCH v2 3/3] arm64: dts: renesas: rzg3e-smarc-som: Enable eth{0-1} (GBETH) interfaces
2025-06-19 8:59 ` Lad, Prabhakar
@ 2025-06-19 11:09 ` John Madieu
0 siblings, 0 replies; 19+ messages in thread
From: John Madieu @ 2025-06-19 11:09 UTC (permalink / raw)
To: Lad, Prabhakar
Cc: andrew+netdev@lunn.ch, conor+dt@kernel.org, davem@davemloft.net,
edumazet@google.com, geert+renesas@glider.be, krzk+dt@kernel.org,
kuba@kernel.org, pabeni@redhat.com, Prabhakar Mahadev Lad,
robh@kernel.org, Biju Das, devicetree@vger.kernel.org,
john.madieu@gmail.com, linux-kernel@vger.kernel.org,
linux-renesas-soc@vger.kernel.org, magnus.damm@gmail.com,
netdev@vger.kernel.org
Hi Prabhakar,
> -----Original Message-----
> From: Lad, Prabhakar <prabhakar.csengg@gmail.com>
> Sent: Thursday, June 19, 2025 11:00 AM
> To: John Madieu <john.madieu.xa@bp.renesas.com>
> Subject: Re: [PATCH v2 3/3] arm64: dts: renesas: rzg3e-smarc-som: Enable
> eth{0-1} (GBETH) interfaces
>
> Hi John,
>
> Thank you for the patch.
>
> On Wed, Jun 11, 2025 at 7:20 AM John Madieu
> <john.madieu.xa@bp.renesas.com> wrote:
> >
> > Enable the Gigabit Ethernet Interfaces (GBETH) populated on the RZ/G3E
> > SMARC EVK
> >
> > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> > Tested-by: Biju Das <biju.das.jz@bp.renesas.com>
> > Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
> > ---
> > .../boot/dts/renesas/rzg3e-smarc-som.dtsi | 106 ++++++++++++++++++
> > 1 file changed, 106 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
> > b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
> > index f99a09d04ddd..4b4c7f3381ad 100644
> > --- a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
> > @@ -26,6 +26,8 @@ / {
> > compatible = "renesas,rzg3e-smarcm", "renesas,r9a09g047e57",
> > "renesas,r9a09g047";
> >
> > aliases {
> > + ethernet0 = ð0;
> > + ethernet1 = ð1;
> > i2c2 = &i2c2;
> > mmc0 = &sdhi0;
> > mmc2 = &sdhi2;
> > @@ -77,6 +79,74 @@ &audio_extal_clk {
> > clock-frequency = <48000000>;
> > };
> >
> > +ð0 {
> > + phy-handle = <&phy0>;
> > + phy-mode = "rgmii-id";
> > +
> > + pinctrl-0 = <ð0_pins>;
> > + pinctrl-names = "default";
> > + status = "okay";
> > +
> > + mdio {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + compatible = "snps,dwmac-mdio";
> > +
> > + phy0: ethernet-phy@7 {
> > + compatible = "ethernet-phy-id0022.1640",
> > + "ethernet-phy-ieee802.3-c22";
> > + reg = <7>;
> > + interrupts-extended = <&icu 3
> IRQ_TYPE_LEVEL_LOW>;
> > + rxc-skew-psec = <1400>;
> > + txc-skew-psec = <1400>;
> > + rxdv-skew-psec = <0>;
> > + txdv-skew-psec = <0>;
> > + rxd0-skew-psec = <0>;
> > + rxd1-skew-psec = <0>;
> > + rxd2-skew-psec = <0>;
> > + rxd3-skew-psec = <0>;
> > + txd0-skew-psec = <0>;
> > + txd1-skew-psec = <0>;
> > + txd2-skew-psec = <0>;
> > + txd3-skew-psec = <0>;
> > + };
> > + };
> > +};
> > +
> > +ð1 {
> > + phy-handle = <&phy1>;
> > + phy-mode = "rgmii-id";
> > +
> > + pinctrl-0 = <ð1_pins>;
> > + pinctrl-names = "default";
> > + status = "okay";
> > +
> > + mdio {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + compatible = "snps,dwmac-mdio";
> > +
> > + phy1: ethernet-phy@7 {
> > + compatible = "ethernet-phy-id0022.1640",
> > + "ethernet-phy-ieee802.3-c22";
> > + reg = <7>;
> > + interrupts-extended = <&icu 16
> IRQ_TYPE_LEVEL_LOW>;
> > + rxc-skew-psec = <1400>;
> > + txc-skew-psec = <1400>;
> > + rxdv-skew-psec = <0>;
> > + txdv-skew-psec = <0>;
> > + rxd0-skew-psec = <0>;
> > + rxd1-skew-psec = <0>;
> > + rxd2-skew-psec = <0>;
> > + rxd3-skew-psec = <0>;
> > + txd0-skew-psec = <0>;
> > + txd1-skew-psec = <0>;
> > + txd2-skew-psec = <0>;
> > + txd3-skew-psec = <0>;
> > + };
> > + };
> > +};
> > +
> > &gpu {
> > status = "okay";
> > mali-supply = <®_vdd0p8v_others>; @@ -103,6 +173,42 @@
> > raa215300: pmic@12 { };
> >
> > &pinctrl {
> > + eth0_pins: eth0 {
> > + pinmux = <RZG3E_PORT_PINMUX(A, 1, 1)>, /* MDC */
> > + <RZG3E_PORT_PINMUX(A, 0, 1)>, /* MDIO */
> > + <RZG3E_PORT_PINMUX(C, 2, 15)>, /* PHY_INTR
> (IRQ2) */
> > + <RZG3E_PORT_PINMUX(C, 1, 1)>, /* RXD3 */
> > + <RZG3E_PORT_PINMUX(C, 0, 1)>, /* RXD2 */
> > + <RZG3E_PORT_PINMUX(B, 7, 1)>, /* RXD1 */
> > + <RZG3E_PORT_PINMUX(B, 6, 1)>, /* RXD0 */
> > + <RZG3E_PORT_PINMUX(B, 0, 1)>, /* RXC */
> > + <RZG3E_PORT_PINMUX(A, 2, 1)>, /* RX_CTL */
> > + <RZG3E_PORT_PINMUX(B, 5, 1)>, /* TXD3 */
> > + <RZG3E_PORT_PINMUX(B, 4, 1)>, /* TXD2 */
> > + <RZG3E_PORT_PINMUX(B, 3, 1)>, /* TXD1 */
> > + <RZG3E_PORT_PINMUX(B, 2, 1)>, /* TXD0 */
> > + <RZG3E_PORT_PINMUX(B, 1, 1)>, /* TXC */
> > + <RZG3E_PORT_PINMUX(A, 3, 1)>; /* TX_CTL */
> like RZ/V2H on RZ/G3E PFC_OEN BITS(0,1) need to be configured based on
> RGMII/MII mode?
Yes, it is the case. OEN1 and OEN0.
>
> Cheers,
> Prabhakar
Regards,
John
>
> > + };
> > +
> > + eth1_pins: eth1 {
> > + pinmux = <RZG3E_PORT_PINMUX(D, 1, 1)>, /* MDC */
> > + <RZG3E_PORT_PINMUX(D, 0, 1)>, /* MDIO */
> > + <RZG3E_PORT_PINMUX(F, 2, 15)>, /* PHY_INTR
> (IRQ15) */
> > + <RZG3E_PORT_PINMUX(F, 1, 1)>, /* RXD3 */
> > + <RZG3E_PORT_PINMUX(F, 0, 1)>, /* RXD2 */
> > + <RZG3E_PORT_PINMUX(E, 7, 1)>, /* RXD1 */
> > + <RZG3E_PORT_PINMUX(E, 6, 1)>, /* RXD0 */
> > + <RZG3E_PORT_PINMUX(E, 0, 1)>, /* RXC */
> > + <RZG3E_PORT_PINMUX(D, 2, 1)>, /* RX_CTL */
> > + <RZG3E_PORT_PINMUX(E, 5, 1)>, /* TXD3 */
> > + <RZG3E_PORT_PINMUX(E, 4, 1)>, /* TXD2 */
> > + <RZG3E_PORT_PINMUX(E, 3, 1)>, /* TXD1 */
> > + <RZG3E_PORT_PINMUX(E, 2, 1)>, /* TXD0 */
> > + <RZG3E_PORT_PINMUX(E, 1, 1)>, /* TXC */
> > + <RZG3E_PORT_PINMUX(D, 3, 1)>; /* TX_CTL */
> > + };
> > +
> > i2c2_pins: i2c {
> > pinmux = <RZG3E_PORT_PINMUX(3, 4, 1)>, /* SCL2 */
> > <RZG3E_PORT_PINMUX(3, 5, 1)>; /* SDA2 */
> > --
> > 2.25.1
> >
> >
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v2 0/3] Add support for GBETH IPs found on RZ/G3E SoCs
2025-06-11 6:16 [PATCH v2 0/3] Add support for GBETH IPs found on RZ/G3E SoCs John Madieu
` (2 preceding siblings ...)
2025-06-11 6:16 ` [PATCH v2 3/3] arm64: dts: renesas: rzg3e-smarc-som: Enable eth{0-1} (GBETH) interfaces John Madieu
@ 2025-06-12 20:12 ` Rob Herring (Arm)
3 siblings, 0 replies; 19+ messages in thread
From: Rob Herring (Arm) @ 2025-06-12 20:12 UTC (permalink / raw)
To: John Madieu
Cc: kuba, krzk+dt, john.madieu, linux-kernel, geert+renesas, davem,
pabeni, linux-renesas-soc, netdev, prabhakar.mahadev-lad.rj,
conor+dt, biju.das.jz, magnus.damm, edumazet, devicetree,
andrew+netdev
On Wed, 11 Jun 2025 08:16:06 +0200, John Madieu wrote:
> Hi all,
>
> This series adds support for the two Gigabit Ethernet (GBETH) interfaces on the
> Renesas RZ/G3E (R9A09G047) SoCs and their enablement on the SMARC-II EVK. This
> is achieved by integrating the necessary clock/reset signals prior to defining
> common DTS nodes, and enabling both GBETH ports at the board level.
>
> Here are pach dependencies:
>
> - Patch 1/3 is based on renesas-drivers tree, on top of renesas-clk-for-v6.17
> branch
> - Patches [2,3]/3 are based on renesas-devel tree, on top of
> renesas-dts-for-v6.17 branch
>
> V1 of this series is located here [1]. It originaly included a patch for binding
> documentation, which, in response to Jakub [2], has been resubmited as a
> standalone patch for net-next.
>
> Changes in v2:
> - Appart from resending the patches and some collected tags, there is no changes in V2.
> - Separated binding patch send as standalone patch can be found here [3]
>
> Below are some test logs, involving pings, then unbind/bind, then pings again:
>
> ```
> root@smarc-rzg3e:~# ping -I eth0 google.com
> PING google.com (172.217.20.174) from 192.168.1.245 eth0: 56(84) bytes of data.
> 64 bytes from waw02s07-in-f14.1e100.net (172.217.20.174): icmp_seq=1 ttl=117 time=4.42 ms
> 64 bytes from waw02s07-in-f14.1e100.net (172.217.20.174): icmp_seq=2 ttl=117 time=3.87 ms
> 64 bytes from waw02s07-in-f14.1e100.net (172.217.20.174): icmp_seq=3 ttl=117 time=3.68 ms
> 64 bytes from waw02s07-in-f14.1e100.net (172.217.20.174): icmp_seq=4 ttl=117 time=3.83 ms
> ^C
> --- google.com ping statistics ---
> 4 packets transmitted, 4 received, 0% packet loss, time 3005ms
> rtt min/avg/max/mdev = 3.680/3.949/4.415/0.278 ms
> root@smarc-rzg3e:~#
>
> root@smarc-rzg3e:~# ping -I eth1 google.com
> PING google.com (142.250.75.238) from 192.168.1.242 eth1: 56(84) bytes of data.
> 64 bytes from par10s41-in-f14.1e100.net (142.250.75.238): icmp_seq=1 ttl=251 time=4.72 ms
> 64 bytes from par10s41-in-f14.1e100.net (142.250.75.238): icmp_seq=2 ttl=251 time=4.34 ms
> 64 bytes from par10s41-in-f14.1e100.net (142.250.75.238): icmp_seq=3 ttl=251 time=5.66 ms
> ^C
> --- google.com ping statistics ---
> 3 packets transmitted, 3 received, 0% packet loss, time 2003ms
> rtt min/avg/max/mdev = 4.338/4.904/5.659/0.555 ms
> root@smarc-rzg3e:~#
> root@smarc-rzg3e:~#
> root@smarc-rzg3e:~#
> root@smarc-rzg3e:~# echo "15c40000.ethernet" > /sys/bus/platform/drivers/renesas-gbeth/bind
> [ 413.422009] renesas-gbeth 15c40000.ethernet: IRQ sfty not found
> [ 413.429570] renesas-gbeth 15c40000.ethernet: User ID: 0x0, Synopsys ID: 0x52
> [ 413.436749] renesas-gbeth 15c40000.ethernet: DWMAC4/5
> [ 413.441974] renesas-gbeth 15c40000.ethernet: DMA HW capability register supported
> [ 413.449536] renesas-gbeth 15c40000.ethernet: RX Checksum Offload Engine supported
> [ 413.457098] renesas-gbeth 15c40000.ethernet: Wake-Up On Lan supported
> [ 413.463617] renesas-gbeth 15c40000.ethernet: Enable RX Mitigation via HW Watchdog Timer
> [ 413.471807] renesas-gbeth 15c40000.ethernet: Enabled L3L4 Flow TC (entries=8)
> [ 413.478982] renesas-gbeth 15c40000.ethernet: Enabled RFS Flow TC (entries=10)
> [ 413.486148] renesas-gbeth 15c40000.ethernet: Using 32/32 bits DMA host/device width
> [ 413.523040] renesas-gbeth 15c40000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-0
> [ 413.534875] renesas-gbeth 15c40000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-1
> [ 413.546218] renesas-gbeth 15c40000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-2
> [ 413.556666] renesas-gbeth 15c40000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-3
> [ 413.633799] renesas-gbeth 15c40000.ethernet eth0: PHY [stmmac-1:07] driver [Microchip KSZ9131 Gigabit PHY] (irq=27)
> [ 413.659645] dwmac4: Master AXI performs fixed burst length
> [ 413.666549] renesas-gbeth 15c40000.ethernet eth0: No Safety Features support found
> [ 413.674263] renesas-gbeth 15c40000.ethernet eth0: IEEE 1588-2008 Advanced Timestamp supported
> [ 413.683733] renesas-gbeth 15c40000.ethernet eth0: registered PTP clock
> [ 413.695546] renesas-gbeth 15c40000.ethernet eth0: configuring for phy/rgmii-id link mode
> [ 416.576645] renesas-gbeth 15c40000.ethernet eth0: Link is Up - 1Gbps/Full - flow control off
> root@smarc-rzg3e:~#
> root@smarc-rzg3e:~# echo "15c30000.ethernet" > /sys/bus/platform/drivers/renesas-gbeth/bind
> [ 430.269771] renesas-gbeth 15c30000.ethernet: IRQ sfty not found
> [ 430.277347] renesas-gbeth 15c30000.ethernet: User ID: 0x1, Synopsys ID: 0x52
> [ 430.284525] renesas-gbeth 15c30000.ethernet: DWMAC4/5
> [ 430.289753] renesas-gbeth 15c30000.ethernet: DMA HW capability register supported
> [ 430.297317] renesas-gbeth 15c30000.ethernet: RX Checksum Offload Engine supported
> [ 430.304880] renesas-gbeth 15c30000.ethernet: Wake-Up On Lan supported
> [ 430.311400] renesas-gbeth 15c30000.ethernet: Enable RX Mitigation via HW Watchdog Timer
> [ 430.319598] renesas-gbeth 15c30000.ethernet: Enabled L3L4 Flow TC (entries=8)
> [ 430.326774] renesas-gbeth 15c30000.ethernet: Enabled RFS Flow TC (entries=10)
> [ 430.333942] renesas-gbeth 15c30000.ethernet: Using 32/32 bits DMA host/device width
> [ 430.360549] renesas-gbeth 15c30000.ethernet eth1: Register MEM_TYPE_PAGE_POOL RxQ-0
> [ 432.366627] renesas-gbeth 15c30000.ethernet eth1: Register MEM_TYPE_PAGE_POOL RxQ-1
> [ 432.377218] renesas-gbeth 15c30000.ethernet eth1: Register MEM_TYPE_PAGE_POOL RxQ-2
> [ 432.386450] renesas-gbeth 15c30000.ethernet eth1: Register MEM_TYPE_PAGE_POOL RxQ-3
> [ 432.461470] renesas-gbeth 15c30000.ethernet eth1: PHY [stmmac-0:07] driver [Microchip KSZ9131 Gigabit PHY] (irq=23)
> [ 432.487523] dwmac4: Master AXI performs fixed burst length
> [ 432.494429] renesas-gbeth 15c30000.ethernet eth1: No Safety Features support found
> [ 432.502149] renesas-gbeth 15c30000.ethernet eth1: IEEE 1588-2008 Advanced Timestamp supported
> [ 432.511638] renesas-gbeth 15c30000.ethernet eth1: registered PTP clock
> [ 432.523033] renesas-gbeth 15c30000.ethernet eth1: configuring for phy/rgmii-id link mode
> [ 435.489601] renesas-gbeth 15c30000.ethernet eth1: Link is Up - 1Gbps/Full - flow control off
> root@smarc-rzg3e:~#
> root@smarc-rzg3e:~#
> root@smarc-rzg3e:~# ping -I eth0 google.com
> PING google.com (142.250.75.238) from 192.168.1.242 eth0: 56(84) bytes of data.
> 64 bytes from par10s41-in-f14.1e100.net (142.250.75.238): icmp_seq=1 ttl=251 time=4.62 ms
> 64 bytes from par10s41-in-f14.1e100.net (142.250.75.238): icmp_seq=2 ttl=251 time=4.19 ms
> 64 bytes from par10s41-in-f14.1e100.net (142.250.75.238): icmp_seq=3 ttl=251 time=4.49 ms
> 64 bytes from par10s41-in-f14.1e100.net (142.250.75.238): icmp_seq=4 ttl=251 time=4.76 ms
> ^C
> --- google.com ping statistics ---
> 4 packets transmitted, 4 received, 0% packet loss, time 3005ms
> rtt min/avg/max/mdev = 4.189/4.514/4.758/0.210 ms
> root@smarc-rzg3e:~# ping -I eth1 google.com
> PING google.com (142.250.75.238) from 192.168.1.245 eth1: 56(84) bytes of data.
> 64 bytes from par10s41-in-f14.1e100.net (142.250.75.238): icmp_seq=1 ttl=251 time=4.45 ms
> 64 bytes from par10s41-in-f14.1e100.net (142.250.75.238): icmp_seq=2 ttl=251 time=4.79 ms
> 64 bytes from par10s41-in-f14.1e100.net (142.250.75.238): icmp_seq=3 ttl=251 time=4.42 ms
> 64 bytes from par10s41-in-f14.1e100.net (142.250.75.238): icmp_seq=4 ttl=251 time=4.47 ms
> ^C
> --- google.com ping statistics ---
> 4 packets transmitted, 4 received, 0% packet loss, time 3005ms
> rtt min/avg/max/mdev = 4.417/4.530/4.787/0.149 ms
> root@smarc-rzg3e:~#
> ```
>
> [1] - https://lore.kernel.org/all/20250604065200.163778-1-john.madieu.xa@bp.renesas.com/
> [2] - https://lore.kernel.org/all/20250609083008.0157fe47@kernel.org/
> [3] - https://lore.kernel.org/all/20250611061204.15393-1-john.madieu.xa@bp.renesas.com/
>
> Regards,
> John Madieu
>
> John Madieu (3):
> clk: renesas: r9a09g047: Add clock and reset signals for the GBETH IPs
> arm64: dts: renesas: r9a09g047: Add GBETH nodes
> arm64: dts: renesas: rzg3e-smarc-som: Enable eth{0-1} (GBETH)
> interfaces
>
> arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 207 ++++++++++++++++++
> .../boot/dts/renesas/rzg3e-smarc-som.dtsi | 106 +++++++++
> drivers/clk/renesas/r9a09g047-cpg.c | 64 ++++++
> 3 files changed, 377 insertions(+)
>
> --
> 2.25.1
>
>
>
My bot found new DTB warnings on the .dts files added or changed in this
series.
Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not. No need to reply
unless the platform maintainer has comments.
If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:
pip3 install dtschema --upgrade
This patch series was applied (using b4) to base:
Base: attempting to guess base-commit...
Base: tags/v6.16-rc1-15-gc3303e716218 (exact match)
If this is not the correct base, please add 'base-commit' tag
(or use b4 which does this automatically)
New warnings running 'make CHECK_DTBS=y for arch/arm64/boot/dts/renesas/' for 20250611061609.15527-1-john.madieu.xa@bp.renesas.com:
arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dtb: ethernet@15c30000 (renesas,r9a09g047-gbeth): compatible:0: 'renesas,r9a09g047-gbeth' is not one of ['renesas,r9a09g056-gbeth', 'renesas,r9a09g057-gbeth']
from schema $id: http://devicetree.org/schemas/net/renesas,r9a09g057-gbeth.yaml#
arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dtb: ethernet@15c40000 (renesas,r9a09g047-gbeth): compatible:0: 'renesas,r9a09g047-gbeth' is not one of ['renesas,r9a09g056-gbeth', 'renesas,r9a09g057-gbeth']
from schema $id: http://devicetree.org/schemas/net/renesas,r9a09g057-gbeth.yaml#
^ permalink raw reply [flat|nested] 19+ messages in thread