[PATCH v3 0/3] Add support for GBETH IPs found on RZ/G3E SoCs

[PATCH v3 0/3] Add support for GBETH IPs found on RZ/G3E SoCs

[John Madieu]

Hi all,

This series adds support for the two Gigabit Ethernet (GBETH) interfaces on the
Renesas RZ/G3E (R9A09G047) SoCs and their enablement on the SMARC-II EVK. This
is achieved by integrating the necessary clock/reset signals prior to defining
common DTS nodes, and enabling both GBETH ports at the board level.

Here are pach dependencies:

 - Patch 1/3 is based on renesas-drivers tree, on top of renesas-clk-for-v6.17
 branch
 - Patches [2,3]/3  are based on renesas-devel tree, on top of
 renesas-dts-for-v6.17 branch

V1 of this series is located here [1]. It originaly included a patch for
binding documentation, which, in response to Jakub [2], has been resubmited
as a standalone patch for net-next.

V2 can be found here [3].

Changes in v2:
 - Appart from resending the patches and some collected tags, there is no
 changes in V2.
 - Separated binding patch send as standalone patch can be found here [4]

Changes in v3:
 - Fixed consistency with clock names, replacing dashes with underscores
 - Labeled mdio nodes and used phandle-based override instead of node
 redefinition
 - Minor typo fixes

Note for DT maintainers:
Documentation/dt-bindings patch was sent separately and has already been applied here [5]

[1] - https://lore.kernel.org/all/20250604065200.163778-1-john.madieu.xa@bp.renesas.com/
[2] - https://lore.kernel.org/all/20250609083008.0157fe47@kernel.org/
[3] - https://lore.kernel.org/all/20250611061609.15527-1-john.madieu.xa@bp.renesas.com/
[4] - https://lore.kernel.org/all/20250611061204.15393-1-john.madieu.xa@bp.renesas.com/
[5] - https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next.git/commit/?id=31b928210df1097eaa5e8cb51e2ff79989ebe57e

Regards,
John Madieu

John Madieu (3):
  clk: renesas: r9a09g047: Add clock and reset signals for the GBETH IPs
  arm64: dts: renesas: r9a09g047: Add GBETH nodes
  arm64: dts: renesas: rzg3e-smarc-som: Enable eth{0-1} (GBETH)
    interfaces

 arch/arm64/boot/dts/renesas/r9a09g047.dtsi    | 207 ++++++++++++++++++
 .../boot/dts/renesas/rzg3e-smarc-som.dtsi     |  98 +++++++++
 drivers/clk/renesas/r9a09g047-cpg.c           |  64 ++++++
 3 files changed, 369 insertions(+)

-- 
2.25.1

[PATCH v3 1/3] clk: renesas: r9a09g047: Add clock and reset signals for the GBETH IPs

[John Madieu]

Add clock and reset entries for the Gigabit Ethernet Interfaces (GBETH 0-1)
IPs found on the RZ/G3E SoC. This includes various PLLs, dividers, and mux
clocks needed by these two GBETH IPs.

Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Tested-by: Biju Das <biju.das.jz@bp.renesas.com>
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---

v2:
No changes but resending without dt-bindings patch

v3: 
Uses underscores instead of dashes in clock names

 drivers/clk/renesas/r9a09g047-cpg.c | 64 +++++++++++++++++++++++++++++
 1 file changed, 64 insertions(+)

diff --git a/drivers/clk/renesas/r9a09g047-cpg.c b/drivers/clk/renesas/r9a09g047-cpg.c
index 21699999cedd..41bae823a0c6 100644
--- a/drivers/clk/renesas/r9a09g047-cpg.c
+++ b/drivers/clk/renesas/r9a09g047-cpg.c
@@ -29,6 +29,7 @@ enum clk_ids {
 	CLK_PLLDTY,
 	CLK_PLLCA55,
 	CLK_PLLVDO,
+	CLK_PLLETH,
 
 	/* Internal Core Clocks */
 	CLK_PLLCM33_DIV3,
@@ -46,6 +47,15 @@ enum clk_ids {
 	CLK_PLLDTY_ACPU,
 	CLK_PLLDTY_ACPU_DIV2,
 	CLK_PLLDTY_ACPU_DIV4,
+	CLK_PLLDTY_DIV8,
+	CLK_PLLETH_DIV_250_FIX,
+	CLK_PLLETH_DIV_125_FIX,
+	CLK_CSDIV_PLLETH_GBE0,
+	CLK_CSDIV_PLLETH_GBE1,
+	CLK_SMUX2_GBE0_TXCLK,
+	CLK_SMUX2_GBE0_RXCLK,
+	CLK_SMUX2_GBE1_TXCLK,
+	CLK_SMUX2_GBE1_RXCLK,
 	CLK_PLLDTY_DIV16,
 	CLK_PLLVDO_CRU0,
 	CLK_PLLVDO_GPU,
@@ -85,7 +95,18 @@ static const struct clk_div_table dtable_2_64[] = {
 	{0, 0},
 };
 
+static const struct clk_div_table dtable_2_100[] = {
+	{0, 2},
+	{1, 10},
+	{2, 100},
+	{0, 0},
+};
+
 /* Mux clock tables */
+static const char * const smux2_gbe0_rxclk[] = { ".plleth_gbe0", "et0_rxc_rx_clk" };
+static const char * const smux2_gbe0_txclk[] = { ".plleth_gbe0", "et0_txc_tx_clk" };
+static const char * const smux2_gbe1_rxclk[] = { ".plleth_gbe1", "et1_rxc_rx_clk" };
+static const char * const smux2_gbe1_txclk[] = { ".plleth_gbe1", "et1_txc_tx_clk" };
 static const char * const smux2_xspi_clk0[] = { ".pllcm33_div3", ".pllcm33_div4" };
 static const char * const smux2_xspi_clk1[] = { ".smux2_xspi_clk0", ".pllcm33_div5" };
 
@@ -100,6 +121,7 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
 	DEF_FIXED(".pllcln", CLK_PLLCLN, CLK_QEXTAL, 200, 3),
 	DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3),
 	DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLLCA55),
+	DEF_FIXED(".plleth", CLK_PLLETH, CLK_QEXTAL, 125, 3),
 	DEF_FIXED(".pllvdo", CLK_PLLVDO, CLK_QEXTAL, 105, 2),
 
 	/* Internal Core Clocks */
@@ -122,6 +144,18 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
 	DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dtable_2_64),
 	DEF_FIXED(".plldty_acpu_div2", CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU, 1, 2),
 	DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4),
+	DEF_FIXED(".plldty_div8", CLK_PLLDTY_DIV8, CLK_PLLDTY, 1, 8),
+
+	DEF_FIXED(".plleth_250_fix", CLK_PLLETH_DIV_250_FIX, CLK_PLLETH, 1, 4),
+	DEF_FIXED(".plleth_125_fix", CLK_PLLETH_DIV_125_FIX, CLK_PLLETH_DIV_250_FIX, 1, 2),
+	DEF_CSDIV(".plleth_gbe0", CLK_CSDIV_PLLETH_GBE0, CLK_PLLETH_DIV_250_FIX,
+		  CSDIV0_DIVCTL0, dtable_2_100),
+	DEF_CSDIV(".plleth_gbe1", CLK_CSDIV_PLLETH_GBE1, CLK_PLLETH_DIV_250_FIX,
+		  CSDIV0_DIVCTL1, dtable_2_100),
+	DEF_SMUX(".smux2_gbe0_txclk", CLK_SMUX2_GBE0_TXCLK, SSEL0_SELCTL2, smux2_gbe0_txclk),
+	DEF_SMUX(".smux2_gbe0_rxclk", CLK_SMUX2_GBE0_RXCLK, SSEL0_SELCTL3, smux2_gbe0_rxclk),
+	DEF_SMUX(".smux2_gbe1_txclk", CLK_SMUX2_GBE1_TXCLK, SSEL1_SELCTL0, smux2_gbe1_txclk),
+	DEF_SMUX(".smux2_gbe1_rxclk", CLK_SMUX2_GBE1_RXCLK, SSEL1_SELCTL1, smux2_gbe1_rxclk),
 	DEF_FIXED(".plldty_div16", CLK_PLLDTY_DIV16, CLK_PLLDTY, 1, 16),
 
 	DEF_DDIV(".pllvdo_cru0", CLK_PLLVDO_CRU0, CLK_PLLVDO, CDDIV3_DIVCTL3, dtable_2_4),
@@ -139,6 +173,10 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
 		 CDDIV1_DIVCTL3, dtable_1_8),
 	DEF_FIXED("iotop_0_shclk", R9A09G047_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1),
 	DEF_FIXED("spi_clk_spi", R9A09G047_SPI_CLK_SPI, CLK_PLLCM33_XSPI, 1, 2),
+	DEF_FIXED("gbeth_0_clk_ptp_ref_i", R9A09G047_GBETH_0_CLK_PTP_REF_I,
+		  CLK_PLLETH_DIV_125_FIX, 1, 1),
+	DEF_FIXED("gbeth_1_clk_ptp_ref_i", R9A09G047_GBETH_1_CLK_PTP_REF_I,
+		  CLK_PLLETH_DIV_125_FIX, 1, 1),
 };
 
 static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
@@ -214,6 +252,30 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
 						BUS_MSTOP(8, BIT(4))),
 	DEF_MOD("sdhi_2_aclk",			CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14,
 						BUS_MSTOP(8, BIT(4))),
+	DEF_MOD("gbeth_0_clk_tx_i",		CLK_SMUX2_GBE0_TXCLK, 11, 8, 5, 24,
+						BUS_MSTOP(8, BIT(5))),
+	DEF_MOD("gbeth_0_clk_rx_i",		CLK_SMUX2_GBE0_RXCLK, 11, 9, 5, 25,
+						BUS_MSTOP(8, BIT(5))),
+	DEF_MOD("gbeth_0_clk_tx_180_i",		CLK_SMUX2_GBE0_TXCLK, 11, 10, 5, 26,
+						BUS_MSTOP(8, BIT(5))),
+	DEF_MOD("gbeth_0_clk_rx_180_i",		CLK_SMUX2_GBE0_RXCLK, 11, 11, 5, 27,
+						BUS_MSTOP(8, BIT(5))),
+	DEF_MOD("gbeth_0_aclk_csr_i",		CLK_PLLDTY_DIV8, 11, 12, 5, 28,
+						BUS_MSTOP(8, BIT(5))),
+	DEF_MOD("gbeth_0_aclk_i",		CLK_PLLDTY_DIV8, 11, 13, 5, 29,
+						BUS_MSTOP(8, BIT(5))),
+	DEF_MOD("gbeth_1_clk_tx_i",		CLK_SMUX2_GBE1_TXCLK, 11, 14, 5, 30,
+						BUS_MSTOP(8, BIT(6))),
+	DEF_MOD("gbeth_1_clk_rx_i",		CLK_SMUX2_GBE1_RXCLK, 11, 15, 5, 31,
+						BUS_MSTOP(8, BIT(6))),
+	DEF_MOD("gbeth_1_clk_tx_180_i",		CLK_SMUX2_GBE1_TXCLK, 12, 0, 6, 0,
+						BUS_MSTOP(8, BIT(6))),
+	DEF_MOD("gbeth_1_clk_rx_180_i",		CLK_SMUX2_GBE1_RXCLK, 12, 1, 6, 1,
+						BUS_MSTOP(8, BIT(6))),
+	DEF_MOD("gbeth_1_aclk_csr_i",		CLK_PLLDTY_DIV8, 12, 2, 6, 2,
+						BUS_MSTOP(8, BIT(6))),
+	DEF_MOD("gbeth_1_aclk_i",		CLK_PLLDTY_DIV8, 12, 3, 6, 3,
+						BUS_MSTOP(8, BIT(6))),
 	DEF_MOD("cru_0_aclk",			CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18,
 						BUS_MSTOP(9, BIT(4))),
 	DEF_MOD_NO_PM("cru_0_vclk",		CLK_PLLVDO_CRU0, 13, 3, 6, 19,
@@ -255,6 +317,8 @@ static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
 	DEF_RST(10, 7, 4, 24),		/* SDHI_0_IXRST */
 	DEF_RST(10, 8, 4, 25),		/* SDHI_1_IXRST */
 	DEF_RST(10, 9, 4, 26),		/* SDHI_2_IXRST */
+	DEF_RST(11, 0, 5, 1),		/* GBETH_0_ARESETN_I */
+	DEF_RST(11, 1, 5, 2),		/* GBETH_1_ARESETN_I */
 	DEF_RST(12, 5, 5, 22),		/* CRU_0_PRESETN */
 	DEF_RST(12, 6, 5, 23),		/* CRU_0_ARESETN */
 	DEF_RST(12, 7, 5, 24),		/* CRU_0_S_RESETN */
-- 
2.25.1

[PATCH v3 2/3] arm64: dts: renesas: r9a09g047: Add GBETH nodes

[John Madieu]

Add GBETH nodes to RZ/G3E (R9A09G047) SoC DTSI.

Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Tested-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---

Changes:

v2:
No changes but resending without dt-bindings patch

v3:
Labels mdio nodes

 arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 207 +++++++++++++++++++++
 1 file changed, 207 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
index a0d4fab4fe05..a6a5b1e53e9c 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
@@ -759,6 +759,213 @@ csi2cru: endpoint@0 {
 				};
 			};
 		};
+
+		eth0: ethernet@15c30000 {
+			compatible = "renesas,r9a09g047-gbeth", "renesas,rzv2h-gbeth", "snps,dwmac-5.20";
+			reg = <0 0x15c30000 0 0x10000>;
+			clocks = <&cpg CPG_MOD 0xbd>, <&cpg CPG_MOD 0xbc>,
+				 <&cpg CPG_CORE R9A09G047_GBETH_0_CLK_PTP_REF_I>,
+				 <&cpg CPG_MOD 0xb8>, <&cpg CPG_MOD 0xb9>,
+				 <&cpg CPG_MOD 0xba>, <&cpg CPG_MOD 0xbb>;
+			clock-names = "stmmaceth", "pclk", "ptp_ref",
+				      "tx", "rx", "tx-180", "rx-180";
+			interrupts = <GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 767 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 775 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "macirq", "eth_wake_irq", "eth_lpi",
+					  "rx-queue-0", "rx-queue-1", "rx-queue-2",
+					  "rx-queue-3", "tx-queue-0", "tx-queue-1",
+					  "tx-queue-2", "tx-queue-3";
+			resets = <&cpg 0xb0>;
+			power-domains = <&cpg>;
+			snps,multicast-filter-bins = <256>;
+			snps,perfect-filter-entries = <128>;
+			rx-fifo-depth = <8192>;
+			tx-fifo-depth = <8192>;
+			snps,fixed-burst;
+			snps,no-pbl-x8;
+			snps,force_thresh_dma_mode;
+			snps,axi-config = <&stmmac_axi_setup>;
+			snps,mtl-rx-config = <&mtl_rx_setup0>;
+			snps,mtl-tx-config = <&mtl_tx_setup0>;
+			snps,txpbl = <32>;
+			snps,rxpbl = <32>;
+			status = "disabled";
+
+			mdio0: mdio {
+				compatible = "snps,dwmac-mdio";
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+
+			mtl_rx_setup0: rx-queues-config {
+				snps,rx-queues-to-use = <4>;
+				snps,rx-sched-sp;
+
+				queue0 {
+					snps,dcb-algorithm;
+					snps,priority = <0x1>;
+					snps,map-to-dma-channel = <0>;
+				};
+
+				queue1 {
+					snps,dcb-algorithm;
+					snps,priority = <0x2>;
+					snps,map-to-dma-channel = <1>;
+				};
+
+				queue2 {
+					snps,dcb-algorithm;
+					snps,priority = <0x4>;
+					snps,map-to-dma-channel = <2>;
+				};
+
+				queue3 {
+					snps,dcb-algorithm;
+					snps,priority = <0x8>;
+					snps,map-to-dma-channel = <3>;
+				};
+			};
+
+			mtl_tx_setup0: tx-queues-config {
+				snps,tx-queues-to-use = <4>;
+
+				queue0 {
+					snps,dcb-algorithm;
+					snps,priority = <0x1>;
+				};
+
+				queue1 {
+					snps,dcb-algorithm;
+					snps,priority = <0x2>;
+				};
+
+				queue2 {
+					snps,dcb-algorithm;
+					snps,priority = <0x4>;
+				};
+
+				queue3 {
+					snps,dcb-algorithm;
+					snps,priority = <0x8>;
+				};
+			};
+		};
+
+		eth1: ethernet@15c40000 {
+			compatible = "renesas,r9a09g047-gbeth", "renesas,rzv2h-gbeth", "snps,dwmac-5.20";
+			reg = <0 0x15c40000 0 0x10000>;
+			clocks = <&cpg CPG_MOD 0xc3>, <&cpg CPG_MOD 0xc2>,
+				 <&cpg CPG_CORE R9A09G047_GBETH_1_CLK_PTP_REF_I>,
+				 <&cpg CPG_MOD 0xbe>, <&cpg CPG_MOD 0xbf>,
+				 <&cpg CPG_MOD 0xc0>, <&cpg CPG_MOD 0xc1>;
+			clock-names = "stmmaceth", "pclk", "ptp_ref",
+				      "tx", "rx", "tx-180", "rx-180";
+			interrupts = <GIC_SPI 780 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 789 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 786 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "macirq", "eth_wake_irq", "eth_lpi",
+					  "rx-queue-0", "rx-queue-1", "rx-queue-2",
+					  "rx-queue-3", "tx-queue-0", "tx-queue-1",
+					  "tx-queue-2", "tx-queue-3";
+			resets = <&cpg 0xb1>;
+			power-domains = <&cpg>;
+			snps,multicast-filter-bins = <256>;
+			snps,perfect-filter-entries = <128>;
+			rx-fifo-depth = <8192>;
+			tx-fifo-depth = <8192>;
+			snps,fixed-burst;
+			snps,no-pbl-x8;
+			snps,force_thresh_dma_mode;
+			snps,axi-config = <&stmmac_axi_setup>;
+			snps,mtl-rx-config = <&mtl_rx_setup1>;
+			snps,mtl-tx-config = <&mtl_tx_setup1>;
+			snps,txpbl = <32>;
+			snps,rxpbl = <32>;
+			status = "disabled";
+
+			mdio1: mdio {
+				compatible = "snps,dwmac-mdio";
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+
+			mtl_rx_setup1: rx-queues-config {
+				snps,rx-queues-to-use = <4>;
+				snps,rx-sched-sp;
+
+				queue0 {
+					snps,dcb-algorithm;
+					snps,priority = <0x1>;
+					snps,map-to-dma-channel = <0>;
+				};
+
+				queue1 {
+					snps,dcb-algorithm;
+					snps,priority = <0x2>;
+					snps,map-to-dma-channel = <1>;
+				};
+
+				queue2 {
+					snps,dcb-algorithm;
+					snps,priority = <0x4>;
+					snps,map-to-dma-channel = <2>;
+				};
+
+				queue3 {
+					snps,dcb-algorithm;
+					snps,priority = <0x8>;
+					snps,map-to-dma-channel = <3>;
+				};
+			};
+
+			mtl_tx_setup1: tx-queues-config {
+				snps,tx-queues-to-use = <4>;
+
+				queue0 {
+					snps,dcb-algorithm;
+					snps,priority = <0x1>;
+				};
+
+				queue1 {
+					snps,dcb-algorithm;
+					snps,priority = <0x2>;
+				};
+
+				queue2 {
+					snps,dcb-algorithm;
+					snps,priority = <0x4>;
+				};
+
+				queue3 {
+					snps,dcb-algorithm;
+					snps,priority = <0x8>;
+				};
+			};
+		};
+	};
+
+	stmmac_axi_setup: stmmac-axi-config {
+		snps,lpi_en;
+		snps,wr_osr_lmt = <0xf>;
+		snps,rd_osr_lmt = <0xf>;
+		snps,blen = <16 8 4 0 0 0 0>;
 	};
 
 	timer {
-- 
2.25.1

[PATCH v3 3/3] arm64: dts: renesas: rzg3e-smarc-som: Enable eth{0-1} (GBETH) interfaces

[John Madieu]

Enable the Gigabit Ethernet Interfaces (GBETH) populated on the RZ/G3E SMARC EVK

Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Tested-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---

Changes:

v2:
No changes but resending without dt-bindings patch

v3:
Updates mdio separately, based on phandles instead of node redefinition

 .../boot/dts/renesas/rzg3e-smarc-som.dtsi     | 98 +++++++++++++++++++
 1 file changed, 98 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
index f99a09d04ddd..2281ec05c1f5 100644
--- a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
@@ -26,6 +26,8 @@ / {
 	compatible = "renesas,rzg3e-smarcm", "renesas,r9a09g047e57", "renesas,r9a09g047";
 
 	aliases {
+		ethernet0 = &eth0;
+		ethernet1 = &eth1;
 		i2c2 = &i2c2;
 		mmc0 = &sdhi0;
 		mmc2 = &sdhi2;
@@ -77,6 +79,24 @@ &audio_extal_clk {
 	clock-frequency = <48000000>;
 };
 
+&eth0 {
+	phy-handle = <&phy0>;
+	phy-mode = "rgmii-id";
+
+	pinctrl-0 = <&eth0_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&eth1 {
+	phy-handle = <&phy1>;
+	phy-mode = "rgmii-id";
+
+	pinctrl-0 = <&eth1_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
 &gpu {
 	status = "okay";
 	mali-supply = <&reg_vdd0p8v_others>;
@@ -102,7 +122,85 @@ raa215300: pmic@12 {
 	};
 };
 
+&mdio0 {
+	phy0: ethernet-phy@7 {
+		compatible = "ethernet-phy-id0022.1640",
+			     "ethernet-phy-ieee802.3-c22";
+		reg = <7>;
+		interrupts-extended = <&icu 3 IRQ_TYPE_LEVEL_LOW>;
+		rxc-skew-psec = <1400>;
+		txc-skew-psec = <1400>;
+		rxdv-skew-psec = <0>;
+		txdv-skew-psec = <0>;
+		rxd0-skew-psec = <0>;
+		rxd1-skew-psec = <0>;
+		rxd2-skew-psec = <0>;
+		rxd3-skew-psec = <0>;
+		txd0-skew-psec = <0>;
+		txd1-skew-psec = <0>;
+		txd2-skew-psec = <0>;
+		txd3-skew-psec = <0>;
+	};
+};
+
+&mdio1 {
+	phy1: ethernet-phy@7 {
+		compatible = "ethernet-phy-id0022.1640",
+			     "ethernet-phy-ieee802.3-c22";
+		reg = <7>;
+		interrupts-extended = <&icu 16 IRQ_TYPE_LEVEL_LOW>;
+		rxc-skew-psec = <1400>;
+		txc-skew-psec = <1400>;
+		rxdv-skew-psec = <0>;
+		txdv-skew-psec = <0>;
+		rxd0-skew-psec = <0>;
+		rxd1-skew-psec = <0>;
+		rxd2-skew-psec = <0>;
+		rxd3-skew-psec = <0>;
+		txd0-skew-psec = <0>;
+		txd1-skew-psec = <0>;
+		txd2-skew-psec = <0>;
+		txd3-skew-psec = <0>;
+	};
+};
+
 &pinctrl {
+	eth0_pins: eth0 {
+		pinmux = <RZG3E_PORT_PINMUX(A, 1, 1)>, /* MDC */
+			 <RZG3E_PORT_PINMUX(A, 0, 1)>, /* MDIO */
+			 <RZG3E_PORT_PINMUX(C, 2, 15)>, /* PHY_INTR (IRQ2) */
+			 <RZG3E_PORT_PINMUX(C, 1, 1)>, /* RXD3 */
+			 <RZG3E_PORT_PINMUX(C, 0, 1)>, /* RXD2 */
+			 <RZG3E_PORT_PINMUX(B, 7, 1)>, /* RXD1 */
+			 <RZG3E_PORT_PINMUX(B, 6, 1)>, /* RXD0 */
+			 <RZG3E_PORT_PINMUX(B, 0, 1)>, /* RXC */
+			 <RZG3E_PORT_PINMUX(A, 2, 1)>, /* RX_CTL */
+			 <RZG3E_PORT_PINMUX(B, 5, 1)>, /* TXD3 */
+			 <RZG3E_PORT_PINMUX(B, 4, 1)>, /* TXD2 */
+			 <RZG3E_PORT_PINMUX(B, 3, 1)>, /* TXD1 */
+			 <RZG3E_PORT_PINMUX(B, 2, 1)>, /* TXD0 */
+			 <RZG3E_PORT_PINMUX(B, 1, 1)>, /* TXC */
+			 <RZG3E_PORT_PINMUX(A, 3, 1)>; /* TX_CTL */
+	};
+
+	eth1_pins: eth1 {
+		pinmux = <RZG3E_PORT_PINMUX(D, 1, 1)>, /* MDC */
+			 <RZG3E_PORT_PINMUX(D, 0, 1)>, /* MDIO */
+			 <RZG3E_PORT_PINMUX(F, 2, 15)>, /* PHY_INTR (IRQ15) */
+			 <RZG3E_PORT_PINMUX(F, 1, 1)>, /* RXD3 */
+			 <RZG3E_PORT_PINMUX(F, 0, 1)>, /* RXD2 */
+			 <RZG3E_PORT_PINMUX(E, 7, 1)>, /* RXD1 */
+			 <RZG3E_PORT_PINMUX(E, 6, 1)>, /* RXD0 */
+			 <RZG3E_PORT_PINMUX(E, 0, 1)>, /* RXC */
+			 <RZG3E_PORT_PINMUX(D, 2, 1)>, /* RX_CTL */
+			 <RZG3E_PORT_PINMUX(E, 5, 1)>, /* TXD3 */
+			 <RZG3E_PORT_PINMUX(E, 4, 1)>, /* TXD2 */
+			 <RZG3E_PORT_PINMUX(E, 3, 1)>, /* TXD1 */
+			 <RZG3E_PORT_PINMUX(E, 2, 1)>, /* TXD0 */
+			 <RZG3E_PORT_PINMUX(E, 1, 1)>, /* TXC */
+			 <RZG3E_PORT_PINMUX(D, 3, 1)>; /* TX_CTL */
+	};
+
 	i2c2_pins: i2c {
 		pinmux = <RZG3E_PORT_PINMUX(3, 4, 1)>, /* SCL2 */
 			 <RZG3E_PORT_PINMUX(3, 5, 1)>; /* SDA2 */
-- 
2.25.1

Re: [PATCH v3 1/3] clk: renesas: r9a09g047: Add clock and reset signals for the GBETH IPs

[Geert Uytterhoeven]

Hi John,

On Mon, 23 Jun 2025 at 10:04, John Madieu <john.madieu.xa@bp.renesas.com> wrote:
> Add clock and reset entries for the Gigabit Ethernet Interfaces (GBETH 0-1)
> IPs found on the RZ/G3E SoC. This includes various PLLs, dividers, and mux
> clocks needed by these two GBETH IPs.
>
> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> Tested-by: Biju Das <biju.das.jz@bp.renesas.com>
> Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
> ---
>
> v2:
> No changes but resending without dt-bindings patch
>
> v3:
> Uses underscores instead of dashes in clock names

Thanks for the update!

> --- a/drivers/clk/renesas/r9a09g047-cpg.c
> +++ b/drivers/clk/renesas/r9a09g047-cpg.c

> +
>  /* Mux clock tables */
> +static const char * const smux2_gbe0_rxclk[] = { ".plleth_gbe0", "et0_rxc_rx_clk" };
> +static const char * const smux2_gbe0_txclk[] = { ".plleth_gbe0", "et0_txc_tx_clk" };
> +static const char * const smux2_gbe1_rxclk[] = { ".plleth_gbe1", "et1_rxc_rx_clk" };
> +static const char * const smux2_gbe1_txclk[] = { ".plleth_gbe1", "et1_txc_tx_clk" };

I have to ask you again: these still differ from the similar names used
on RZ/V2H. Is there a reason for that? Will that cause issues later?
Or is this to be sorted out only when the PHY driver will start
supporting these clocks?

>  static const char * const smux2_xspi_clk0[] = { ".pllcm33_div3", ".pllcm33_div4" };
>  static const char * const smux2_xspi_clk1[] = { ".smux2_xspi_clk0", ".pllcm33_div5" };

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v3 3/3] arm64: dts: renesas: rzg3e-smarc-som: Enable eth{0-1} (GBETH) interfaces

[Geert Uytterhoeven]

Hi John,

On Mon, 23 Jun 2025 at 10:04, John Madieu <john.madieu.xa@bp.renesas.com> wrote:
> Enable the Gigabit Ethernet Interfaces (GBETH) populated on the RZ/G3E SMARC EVK
>
> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> Tested-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>

> v3:
> Updates mdio separately, based on phandles instead of node redefinition

Thanks for the update!

> --- a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
> +++ b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi

>  &pinctrl {
> +       eth0_pins: eth0 {
> +               pinmux = <RZG3E_PORT_PINMUX(A, 1, 1)>, /* MDC */
> +                        <RZG3E_PORT_PINMUX(A, 0, 1)>, /* MDIO */
> +                        <RZG3E_PORT_PINMUX(C, 2, 15)>, /* PHY_INTR (IRQ2) */
> +                        <RZG3E_PORT_PINMUX(C, 1, 1)>, /* RXD3 */
> +                        <RZG3E_PORT_PINMUX(C, 0, 1)>, /* RXD2 */
> +                        <RZG3E_PORT_PINMUX(B, 7, 1)>, /* RXD1 */
> +                        <RZG3E_PORT_PINMUX(B, 6, 1)>, /* RXD0 */
> +                        <RZG3E_PORT_PINMUX(B, 0, 1)>, /* RXC */
> +                        <RZG3E_PORT_PINMUX(A, 2, 1)>, /* RX_CTL */
> +                        <RZG3E_PORT_PINMUX(B, 5, 1)>, /* TXD3 */
> +                        <RZG3E_PORT_PINMUX(B, 4, 1)>, /* TXD2 */
> +                        <RZG3E_PORT_PINMUX(B, 3, 1)>, /* TXD1 */
> +                        <RZG3E_PORT_PINMUX(B, 2, 1)>, /* TXD0 */
> +                        <RZG3E_PORT_PINMUX(B, 1, 1)>, /* TXC */
> +                        <RZG3E_PORT_PINMUX(A, 3, 1)>; /* TX_CTL */
> +       };
> +
> +       eth1_pins: eth1 {
> +               pinmux = <RZG3E_PORT_PINMUX(D, 1, 1)>, /* MDC */
> +                        <RZG3E_PORT_PINMUX(D, 0, 1)>, /* MDIO */
> +                        <RZG3E_PORT_PINMUX(F, 2, 15)>, /* PHY_INTR (IRQ15) */
> +                        <RZG3E_PORT_PINMUX(F, 1, 1)>, /* RXD3 */
> +                        <RZG3E_PORT_PINMUX(F, 0, 1)>, /* RXD2 */
> +                        <RZG3E_PORT_PINMUX(E, 7, 1)>, /* RXD1 */
> +                        <RZG3E_PORT_PINMUX(E, 6, 1)>, /* RXD0 */
> +                        <RZG3E_PORT_PINMUX(E, 0, 1)>, /* RXC */
> +                        <RZG3E_PORT_PINMUX(D, 2, 1)>, /* RX_CTL */
> +                        <RZG3E_PORT_PINMUX(E, 5, 1)>, /* TXD3 */
> +                        <RZG3E_PORT_PINMUX(E, 4, 1)>, /* TXD2 */
> +                        <RZG3E_PORT_PINMUX(E, 3, 1)>, /* TXD1 */
> +                        <RZG3E_PORT_PINMUX(E, 2, 1)>, /* TXD0 */
> +                        <RZG3E_PORT_PINMUX(E, 1, 1)>, /* TXC */
> +                        <RZG3E_PORT_PINMUX(D, 3, 1)>; /* TX_CTL */
> +       };
> +
>         i2c2_pins: i2c {
>                 pinmux = <RZG3E_PORT_PINMUX(3, 4, 1)>, /* SCL2 */
>                          <RZG3E_PORT_PINMUX(3, 5, 1)>; /* SDA2 */

Based on the feedback from Prabhakar on v2, I understand this needs to
configure output-enable for the ET0_TXC_TXCLK and ET1_TXC_TXCLK pins,
and to add support for that in the pin control driver first?

[1] https://lore.kernel.org/all/CA+V-a8uizu5MCur_=g5vJyWbWSTSP2J6FkQ89JB8ges7GWdsjg@mail.gmail.com/
Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH v3 3/3] arm64: dts: renesas: rzg3e-smarc-som: Enable eth{0-1} (GBETH) interfaces

[Biju Das]

> -----Original Message-----
> From: Geert Uytterhoeven <geert@linux-m68k.org>
> Sent: 25 June 2025 16:17
> Subject: Re: [PATCH v3 3/3] arm64: dts: renesas: rzg3e-smarc-som: Enable eth{0-1} (GBETH) interfaces
> 
> Hi John,
> 
> On Mon, 23 Jun 2025 at 10:04, John Madieu <john.madieu.xa@bp.renesas.com> wrote:
> > Enable the Gigabit Ethernet Interfaces (GBETH) populated on the RZ/G3E
> > SMARC EVK
> >
> > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> > Tested-by: Biju Das <biju.das.jz@bp.renesas.com>
> > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
> 
> > v3:
> > Updates mdio separately, based on phandles instead of node
> > redefinition
> 
> Thanks for the update!
> 
> > --- a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
> 
> >  &pinctrl {
> > +       eth0_pins: eth0 {
> > +               pinmux = <RZG3E_PORT_PINMUX(A, 1, 1)>, /* MDC */
> > +                        <RZG3E_PORT_PINMUX(A, 0, 1)>, /* MDIO */
> > +                        <RZG3E_PORT_PINMUX(C, 2, 15)>, /* PHY_INTR (IRQ2) */
> > +                        <RZG3E_PORT_PINMUX(C, 1, 1)>, /* RXD3 */
> > +                        <RZG3E_PORT_PINMUX(C, 0, 1)>, /* RXD2 */
> > +                        <RZG3E_PORT_PINMUX(B, 7, 1)>, /* RXD1 */
> > +                        <RZG3E_PORT_PINMUX(B, 6, 1)>, /* RXD0 */
> > +                        <RZG3E_PORT_PINMUX(B, 0, 1)>, /* RXC */
> > +                        <RZG3E_PORT_PINMUX(A, 2, 1)>, /* RX_CTL */
> > +                        <RZG3E_PORT_PINMUX(B, 5, 1)>, /* TXD3 */
> > +                        <RZG3E_PORT_PINMUX(B, 4, 1)>, /* TXD2 */
> > +                        <RZG3E_PORT_PINMUX(B, 3, 1)>, /* TXD1 */
> > +                        <RZG3E_PORT_PINMUX(B, 2, 1)>, /* TXD0 */
> > +                        <RZG3E_PORT_PINMUX(B, 1, 1)>, /* TXC */
> > +                        <RZG3E_PORT_PINMUX(A, 3, 1)>; /* TX_CTL */
> > +       };
> > +
> > +       eth1_pins: eth1 {
> > +               pinmux = <RZG3E_PORT_PINMUX(D, 1, 1)>, /* MDC */
> > +                        <RZG3E_PORT_PINMUX(D, 0, 1)>, /* MDIO */
> > +                        <RZG3E_PORT_PINMUX(F, 2, 15)>, /* PHY_INTR (IRQ15) */
> > +                        <RZG3E_PORT_PINMUX(F, 1, 1)>, /* RXD3 */
> > +                        <RZG3E_PORT_PINMUX(F, 0, 1)>, /* RXD2 */
> > +                        <RZG3E_PORT_PINMUX(E, 7, 1)>, /* RXD1 */
> > +                        <RZG3E_PORT_PINMUX(E, 6, 1)>, /* RXD0 */
> > +                        <RZG3E_PORT_PINMUX(E, 0, 1)>, /* RXC */
> > +                        <RZG3E_PORT_PINMUX(D, 2, 1)>, /* RX_CTL */
> > +                        <RZG3E_PORT_PINMUX(E, 5, 1)>, /* TXD3 */
> > +                        <RZG3E_PORT_PINMUX(E, 4, 1)>, /* TXD2 */
> > +                        <RZG3E_PORT_PINMUX(E, 3, 1)>, /* TXD1 */
> > +                        <RZG3E_PORT_PINMUX(E, 2, 1)>, /* TXD0 */
> > +                        <RZG3E_PORT_PINMUX(E, 1, 1)>, /* TXC */
> > +                        <RZG3E_PORT_PINMUX(D, 3, 1)>; /* TX_CTL */
> > +       };
> > +
> >         i2c2_pins: i2c {
> >                 pinmux = <RZG3E_PORT_PINMUX(3, 4, 1)>, /* SCL2 */
> >                          <RZG3E_PORT_PINMUX(3, 5, 1)>; /* SDA2 */
> 
> Based on the feedback from Prabhakar on v2, I understand this needs to configure output-enable for the
> ET0_TXC_TXCLK and ET1_TXC_TXCLK pins, and to add support for that in the pin control driver first?
> 
> [1] https://lore.kernel.org/all/CA+V-a8uizu5MCur_=g5vJyWbWSTSP2J6FkQ89JB8ges7GWdsjg@mail.gmail.com/

Maybe this could be the reason for RZ/V2H sees clock monitor issue during unbind/bind and RZ/G3E don't see it when
using DEF_MOD macro. Maybe after this change, It may trigger the clock monitor issue on RZ/G3E as well
forcing to use DEF_MOD_EXTERNAL??

Cheers,
Biju

Re: [PATCH v3 2/3] arm64: dts: renesas: r9a09g047: Add GBETH nodes

[Geert Uytterhoeven]

On Mon, 23 Jun 2025 at 10:04, John Madieu <john.madieu.xa@bp.renesas.com> wrote:
> Add GBETH nodes to RZ/G3E (R9A09G047) SoC DTSI.
>
> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> Tested-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>

> v3:
> Labels mdio nodes

Thanks, will queue in renesas-devel for v6.17.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH v3 1/3] clk: renesas: r9a09g047: Add clock and reset signals for the GBETH IPs

[John Madieu]

Hi Geert,

> -----Original Message-----
> From: Geert Uytterhoeven <geert@linux-m68k.org>
> Sent: Wednesday, June 25, 2025 5:13 PM
> To: John Madieu <john.madieu.xa@bp.renesas.com>
> Subject: Re: [PATCH v3 1/3] clk: renesas: r9a09g047: Add clock and reset
> signals for the GBETH IPs
> 
> Hi John,
> 
> On Mon, 23 Jun 2025 at 10:04, John Madieu <john.madieu.xa@bp.renesas.com>
> wrote:
> > Add clock and reset entries for the Gigabit Ethernet Interfaces (GBETH
> > 0-1) IPs found on the RZ/G3E SoC. This includes various PLLs,
> > dividers, and mux clocks needed by these two GBETH IPs.
> >
> > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> > Tested-by: Biju Das <biju.das.jz@bp.renesas.com>
> > Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
> > ---
> >
> > v2:
> > No changes but resending without dt-bindings patch
> >
> > v3:
> > Uses underscores instead of dashes in clock names
> 
> Thanks for the update!
> 
> > --- a/drivers/clk/renesas/r9a09g047-cpg.c
> > +++ b/drivers/clk/renesas/r9a09g047-cpg.c
> 
> > +
> >  /* Mux clock tables */
> > +static const char * const smux2_gbe0_rxclk[] = { ".plleth_gbe0",
> > +"et0_rxc_rx_clk" }; static const char * const smux2_gbe0_txclk[] = {
> > +".plleth_gbe0", "et0_txc_tx_clk" }; static const char * const
> > +smux2_gbe1_rxclk[] = { ".plleth_gbe1", "et1_rxc_rx_clk" }; static
> > +const char * const smux2_gbe1_txclk[] = { ".plleth_gbe1",
> > +"et1_txc_tx_clk" };
> 
> I have to ask you again: these still differ from the similar names used on
> RZ/V2H. Is there a reason for that? Will that cause issues later?
> Or is this to be sorted out only when the PHY driver will start supporting
> these clocks?
> 

I've discussed internally, and names must match. The next version will
then have appropriate names. Sorry for not mentioning it earlier.

> >  static const char * const smux2_xspi_clk0[] = { ".pllcm33_div3",
> > ".pllcm33_div4" };  static const char * const smux2_xspi_clk1[] = {
> > ".smux2_xspi_clk0", ".pllcm33_div5" };
> 
> Gr{oetje,eeting}s,
> 
>                         Geert

Regards,
John

> 
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-
> m68k.org
> 
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like
> that.
>                                 -- Linus Torvalds