[PATCH v1] clk: renesas: r8a779g0: Add ZG clocks

[PATCH v1] clk: renesas: r8a779g0: Add ZG clocks

[Anh Nguyen]

From decde7c45060327ecb24df8218cd58b9ffd3c45d Mon Sep 17 00:00:00 2001
From: Anh Nguyen <anh.nguyen.pv@renesas.com>
Date: Thu, 21 Aug 2025 09:54:00 +0700
Subject: [PATCH 1/2] clk: renesas: r8a779g0: Add ZG clocks

Add ZG related clocks for GSX

Signed-off-by: Anh Nguyen <anh.nguyen.pv@renesas.com>
Reviewed-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
---
 drivers/clk/renesas/r8a779g0-cpg-mssr.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/clk/renesas/r8a779g0-cpg-mssr.c b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
index dc376b683d22..afb86973e771 100644
--- a/drivers/clk/renesas/r8a779g0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
@@ -151,6 +151,7 @@ static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = {
 	DEF_FIXED("dsiref",	R8A779G0_CLK_DSIREF,	CLK_PLL5_DIV4,	48, 1),
 	DEF_DIV6P1("dsiext",	R8A779G0_CLK_DSIEXT,	CLK_PLL5_DIV4,	CPG_DSIEXTCKCR),
 
+	DEF_FIXED("zg",		R8A779G0_CLK_ZG,	CLK_PLL4_DIV2,	2, 1),
 	DEF_GEN4_SDH("sd0h",	R8A779G0_CLK_SD0H,	CLK_SDSRC,	   CPG_SD0CKCR),
 	DEF_GEN4_SD("sd0",	R8A779G0_CLK_SD0,	R8A779G0_CLK_SD0H, CPG_SD0CKCR),
 	DEF_DIV6P1("mso",	R8A779G0_CLK_MSO,	CLK_PLL5_DIV4,	CPG_MSOCKCR),
@@ -163,6 +164,7 @@ static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = {
 };
 
 static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
+	DEF_MOD("rgx",		  0,	R8A779G0_CLK_ZG),
 	DEF_MOD("isp0",		 16,	R8A779G0_CLK_S0D2_VIO),
 	DEF_MOD("isp1",		 17,	R8A779G0_CLK_S0D2_VIO),
 	DEF_MOD("avb0",		211,	R8A779G0_CLK_S0D4_HSC),
-- 
2.34.1

[PATCH v1] arm64: dts: renesas: r8a779g0: Add new gsx node for V4H

[Anh Nguyen]

From 8a8391bc4ceaac5248267851b71c9cce6b5c434a Mon Sep 17 00:00:00 2001
From: Anh Nguyen <anh.nguyen.pv@renesas.com>
Date: Thu, 21 Aug 2025 10:01:30 +0700
Subject: [PATCH 2/2] arm64: dts: renesas: r8a779g0: Add new gsx node for V4H SoC

Add new gsx node to enable GPU for V4H SoC

Signed-off-by: Anh Nguyen <anh.nguyen.pv@renesas.com>
Reviewed-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
---
 arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
index 744b482e9ff3..1913cde3a3c5 100644
--- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
@@ -2121,6 +2121,15 @@ gic: interrupt-controller@f1000000 {
 			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 		};
 
+		gsx: gsx@fd000000 {
+			compatible = "renesas,gsx";
+			reg = <0 0xfd000000 0 0x800000>;
+			interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 0>;
+			power-domains = <&sysc R8A779G0_PD_A23DGB>;
+			resets = <&cpg 0>;
+		};
+
 		csi40: csi2@fe500000 {
 			compatible = "renesas,r8a779g0-csi2";
 			reg = <0 0xfe500000 0 0x40000>;
-- 
2.34.1

Re: [PATCH v1] clk: renesas: r8a779g0: Add ZG clocks

[Geert Uytterhoeven]

Hi Anh,

On Mon, 25 Aug 2025 at 06:33, Anh Nguyen <anh.nguyen.pv@renesas.com> wrote:
> From decde7c45060327ecb24df8218cd58b9ffd3c45d Mon Sep 17 00:00:00 2001
> From: Anh Nguyen <anh.nguyen.pv@renesas.com>
> Date: Thu, 21 Aug 2025 09:54:00 +0700
> Subject: [PATCH 1/2] clk: renesas: r8a779g0: Add ZG clocks
>
> Add ZG related clocks for GSX
>
> Signed-off-by: Anh Nguyen <anh.nguyen.pv@renesas.com>
> Reviewed-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>

Thanks for your patch!

> --- a/drivers/clk/renesas/r8a779g0-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
> @@ -151,6 +151,7 @@ static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = {
>         DEF_FIXED("dsiref",     R8A779G0_CLK_DSIREF,    CLK_PLL5_DIV4,  48, 1),
>         DEF_DIV6P1("dsiext",    R8A779G0_CLK_DSIEXT,    CLK_PLL5_DIV4,  CPG_DSIEXTCKCR),
>
> +       DEF_FIXED("zg",         R8A779G0_CLK_ZG,        CLK_PLL4_DIV2,  2, 1),

According to the documentation, this is not a fixed clock, but uses
a programmable divider in the FRQCRB register.

>         DEF_GEN4_SDH("sd0h",    R8A779G0_CLK_SD0H,      CLK_SDSRC,         CPG_SD0CKCR),
>         DEF_GEN4_SD("sd0",      R8A779G0_CLK_SD0,       R8A779G0_CLK_SD0H, CPG_SD0CKCR),
>         DEF_DIV6P1("mso",       R8A779G0_CLK_MSO,       CLK_PLL5_DIV4,  CPG_MSOCKCR),
> @@ -163,6 +164,7 @@ static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = {
>  };
>
>  static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
> +       DEF_MOD("rgx",            0,    R8A779G0_CLK_ZG),

Perhaps "3dge", to match the documentation?

>         DEF_MOD("isp0",          16,    R8A779G0_CLK_S0D2_VIO),
>         DEF_MOD("isp1",          17,    R8A779G0_CLK_S0D2_VIO),
>         DEF_MOD("avb0",         211,    R8A779G0_CLK_S0D4_HSC),

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v1] arm64: dts: renesas: r8a779g0: Add new gsx node for V4H

[Geert Uytterhoeven]

Hi Anh,

On Mon, 25 Aug 2025 at 06:37, Anh Nguyen <anh.nguyen.pv@renesas.com> wrote:
> From 8a8391bc4ceaac5248267851b71c9cce6b5c434a Mon Sep 17 00:00:00 2001
> From: Anh Nguyen <anh.nguyen.pv@renesas.com>
> Date: Thu, 21 Aug 2025 10:01:30 +0700
> Subject: [PATCH 2/2] arm64: dts: renesas: r8a779g0: Add new gsx node for V4H SoC
>
> Add new gsx node to enable GPU for V4H SoC
>
> Signed-off-by: Anh Nguyen <anh.nguyen.pv@renesas.com>
> Reviewed-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>

Thanks for your patch!

> --- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
> @@ -2121,6 +2121,15 @@ gic: interrupt-controller@f1000000 {
>                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
>                 };
>
> +               gsx: gsx@fd000000 {
> +                       compatible = "renesas,gsx";

This compatible value is not documented.  However, I don't think this
can be used as-is.  I think the property should look like:

    compatible = "renesas,r8a779g0-gpu", "img,img-axm-8-256".

The first step would be to add it to the DT bindings in
Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml.
Furthermore, support for this variant should be added to the driver
under drivers/gpu/drm/imagination/.
And where to get the firmware required to operate the GPU?

> +                       reg = <0 0xfd000000 0 0x800000>;
> +                       interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>;

According to the documentation, there are 8 interrupts?

> +                       clocks = <&cpg CPG_MOD 0>;
> +                       power-domains = <&sysc R8A779G0_PD_A23DGB>;
> +                       resets = <&cpg 0>;
> +               };
> +
>                 csi40: csi2@fe500000 {
>                         compatible = "renesas,r8a779g0-csi2";
>                         reg = <0 0xfe500000 0 0x40000>;

Gr{oetje,eeting}s,

                        Geert


--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds