[PATCH 0/4] Add RZ/G3E GPT clocks and resets

[PATCH 0/4] Add RZ/G3E GPT clocks and resets

[Biju]

From: Biju Das <biju.das.jz@bp.renesas.com>

The RZ/G3E GPT IP has multiple clocks and resets. It has bus and core
clocks. The bus clock is module clock and core clock is sourced from
the bus clock. So add support for module clock as parent reusing the
existing rzv2h_cpg_fixed_mod_status_clk_register().

Biju Das (4):
  clk: renesas: rzv2h: Refactor
    rzv2h_cpg_fixed_mod_status_clk_register()
  clk: renesas: rzv2h: Add support for parent mod clocks
  dt-bindings: clock: renesas,r9a09g047-cpg: Add GPT core clocks
  clk: renesas: r9a09g047: Add GPT clocks and resets

 drivers/clk/renesas/r9a09g047-cpg.c           | 10 ++-
 drivers/clk/renesas/rzv2h-cpg.c               | 74 ++++++++++++-------
 drivers/clk/renesas/rzv2h-cpg.h               | 22 ++++--
 .../dt-bindings/clock/renesas,r9a09g047-cpg.h |  2 +
 4 files changed, 75 insertions(+), 33 deletions(-)

-- 
2.43.0

[PATCH 1/4] clk: renesas: rzv2h: Refactor rzv2h_cpg_fixed_mod_status_clk_register()

[Biju]

From: Biju Das <biju.das.jz@bp.renesas.com>

Refactor rzv2h_cpg_fixed_mod_status_clk_register() for code reuse
when adding support for module clock as parent later.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/clk/renesas/rzv2h-cpg.c | 63 +++++++++++++++++++--------------
 1 file changed, 36 insertions(+), 27 deletions(-)

diff --git a/drivers/clk/renesas/rzv2h-cpg.c b/drivers/clk/renesas/rzv2h-cpg.c
index f468afbb54e2..8511b7154e90 100644
--- a/drivers/clk/renesas/rzv2h-cpg.c
+++ b/drivers/clk/renesas/rzv2h-cpg.c
@@ -451,34 +451,35 @@ rzv2h_clk_ff_mod_status_is_enabled(struct clk_hw *hw)
 }
 
 static struct clk * __init
-rzv2h_cpg_fixed_mod_status_clk_register(const struct cpg_core_clk *core,
-					struct rzv2h_cpg_priv *priv)
+rzv2h_cpg_mod_status_clk_register(struct rzv2h_cpg_priv *priv, const char *name,
+				  const char *parent_clk_name, u16 mult,
+				  u16 div, struct fixed_mod_conf conf)
 {
 	struct rzv2h_ff_mod_status_clk *clk_hw_data;
 	struct clk_init_data init = { };
 	struct clk_fixed_factor *fix;
-	const struct clk *parent;
 	const char *parent_name;
 	int ret;
 
-	WARN_DEBUG(core->parent >= priv->num_core_clks);
-	parent = priv->clks[core->parent];
-	if (IS_ERR(parent))
-		return ERR_CAST(parent);
-
-	parent_name = __clk_get_name(parent);
-	parent = priv->clks[core->parent];
-	if (IS_ERR(parent))
-		return ERR_CAST(parent);
+	if (!priv->ff_mod_status_ops) {
+		priv->ff_mod_status_ops =
+			devm_kzalloc(priv->dev, sizeof(*priv->ff_mod_status_ops), GFP_KERNEL);
+		if (!priv->ff_mod_status_ops)
+			return ERR_PTR(-ENOMEM);
+		memcpy(priv->ff_mod_status_ops, &clk_fixed_factor_ops,
+		       sizeof(const struct clk_ops));
+		priv->ff_mod_status_ops->is_enabled = rzv2h_clk_ff_mod_status_is_enabled;
+	}
 
 	clk_hw_data = devm_kzalloc(priv->dev, sizeof(*clk_hw_data), GFP_KERNEL);
 	if (!clk_hw_data)
 		return ERR_PTR(-ENOMEM);
 
 	clk_hw_data->priv = priv;
-	clk_hw_data->conf = core->cfg.fixed_mod;
+	clk_hw_data->conf = conf;
+	parent_name = parent_clk_name;
 
-	init.name = core->name;
+	init.name = name;
 	init.ops = priv->ff_mod_status_ops;
 	init.flags = CLK_SET_RATE_PARENT;
 	init.parent_names = &parent_name;
@@ -486,8 +487,8 @@ rzv2h_cpg_fixed_mod_status_clk_register(const struct cpg_core_clk *core,
 
 	fix = &clk_hw_data->fix;
 	fix->hw.init = &init;
-	fix->mult = core->mult;
-	fix->div = core->div;
+	fix->mult = mult;
+	fix->div = div;
 
 	ret = devm_clk_hw_register(priv->dev, &clk_hw_data->fix.hw);
 	if (ret)
@@ -496,6 +497,25 @@ rzv2h_cpg_fixed_mod_status_clk_register(const struct cpg_core_clk *core,
 	return clk_hw_data->fix.hw.clk;
 }
 
+static struct clk * __init
+rzv2h_cpg_fixed_mod_status_clk_register(const struct cpg_core_clk *core,
+					struct rzv2h_cpg_priv *priv)
+{
+	const struct clk *parent;
+	const char *parent_name;
+
+	WARN_DEBUG(core->parent >= priv->num_core_clks);
+	parent = priv->clks[core->parent];
+	if (IS_ERR(parent))
+		return ERR_CAST(parent);
+
+	parent_name = __clk_get_name(parent);
+
+	return rzv2h_cpg_mod_status_clk_register(priv, core->name, parent_name,
+						 core->mult, core->div,
+						 core->cfg.fixed_mod);
+}
+
 static struct clk
 *rzv2h_cpg_clk_src_twocell_get(struct of_phandle_args *clkspec,
 			       void *data)
@@ -575,17 +595,6 @@ rzv2h_cpg_register_core_clk(const struct cpg_core_clk *core,
 			clk = clk_hw->clk;
 		break;
 	case CLK_TYPE_FF_MOD_STATUS:
-		if (!priv->ff_mod_status_ops) {
-			priv->ff_mod_status_ops =
-				devm_kzalloc(dev, sizeof(*priv->ff_mod_status_ops), GFP_KERNEL);
-			if (!priv->ff_mod_status_ops) {
-				clk = ERR_PTR(-ENOMEM);
-				goto fail;
-			}
-			memcpy(priv->ff_mod_status_ops, &clk_fixed_factor_ops,
-			       sizeof(const struct clk_ops));
-			priv->ff_mod_status_ops->is_enabled = rzv2h_clk_ff_mod_status_is_enabled;
-		}
 		clk = rzv2h_cpg_fixed_mod_status_clk_register(core, priv);
 		break;
 	case CLK_TYPE_PLL:
-- 
2.43.0

[PATCH 2/4] clk: renesas: rzv2h: Add support for parent mod clocks

[Biju]

From: Biju Das <biju.das.jz@bp.renesas.com>

Add support for parent mod clock to register core clocks that has a
parent module clock on the Renesas RZ/G3E SoC (eg: GPT has two clocks
bus clock and core clock. The core clock is controlled by the bus
clock).

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/clk/renesas/rzv2h-cpg.c | 11 +++++++++++
 drivers/clk/renesas/rzv2h-cpg.h | 22 +++++++++++++++++-----
 2 files changed, 28 insertions(+), 5 deletions(-)

diff --git a/drivers/clk/renesas/rzv2h-cpg.c b/drivers/clk/renesas/rzv2h-cpg.c
index 8511b7154e90..43fd3fadc5f7 100644
--- a/drivers/clk/renesas/rzv2h-cpg.c
+++ b/drivers/clk/renesas/rzv2h-cpg.c
@@ -823,6 +823,17 @@ rzv2h_cpg_register_mod_clk(const struct rzv2h_mod_clk *mod,
 	}
 
 	priv->clks[id] = clock->hw.clk;
+	if (mod->child_name) {
+		WARN_DEBUG(mod->child >= priv->num_core_clks);
+		WARN_DEBUG(PTR_ERR(priv->clks[mod->child]) != -ENOENT);
+
+		clk = rzv2h_cpg_mod_status_clk_register(priv, mod->child_name, mod->name, 1, 1,
+							FIXED_MOD_CONF_PACK(mod->mon_index,
+									    mod->mon_bit));
+		if (IS_ERR_OR_NULL(clk))
+			goto fail;
+		priv->clks[mod->child] = clk;
+	}
 
 	/*
 	 * Ensure the module clocks and MSTOP bits are synchronized when they are
diff --git a/drivers/clk/renesas/rzv2h-cpg.h b/drivers/clk/renesas/rzv2h-cpg.h
index 840eed25aeda..c4205c8fd426 100644
--- a/drivers/clk/renesas/rzv2h-cpg.h
+++ b/drivers/clk/renesas/rzv2h-cpg.h
@@ -235,8 +235,10 @@ enum clk_types {
  */
 struct rzv2h_mod_clk {
 	const char *name;
+	const char *child_name;
 	u32 mstop_data;
 	u16 parent;
+	u16 child;
 	bool critical;
 	bool no_pm;
 	u8 on_index;
@@ -247,11 +249,13 @@ struct rzv2h_mod_clk {
 };
 
 #define DEF_MOD_BASE(_name, _mstop, _parent, _critical, _no_pm, _onindex, \
-		     _onbit, _monindex, _monbit, _ext_clk_mux_index) \
+		     _onbit, _monindex, _monbit, _ext_clk_mux_index, _childname, _child) \
 	{ \
 		.name = (_name), \
+		.child_name = (_childname), \
 		.mstop_data = (_mstop), \
 		.parent = (_parent), \
+		.child = (_child), \
 		.critical = (_critical), \
 		.no_pm = (_no_pm), \
 		.on_index = (_onindex), \
@@ -262,18 +266,26 @@ struct rzv2h_mod_clk {
 	}
 
 #define DEF_MOD(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop) \
-	DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit, -1)
+	DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, \
+		     _monbit, -1, NULL, 0)
 
 #define DEF_MOD_CRITICAL(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop) \
-	DEF_MOD_BASE(_name, _mstop, _parent, true, false, _onindex, _onbit, _monindex, _monbit, -1)
+	DEF_MOD_BASE(_name, _mstop, _parent, true, false, _onindex, _onbit, _monindex, \
+		     _monbit, -1, NULL, 0)
 
 #define DEF_MOD_NO_PM(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop) \
-	DEF_MOD_BASE(_name, _mstop, _parent, false, true, _onindex, _onbit, _monindex, _monbit, -1)
+	DEF_MOD_BASE(_name, _mstop, _parent, false, true, _onindex, _onbit, _monindex, \
+		     _monbit, -1, NULL, 0)
 
 #define DEF_MOD_MUX_EXTERNAL(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop, \
 			     _ext_clk_mux_index) \
 	DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit, \
-		     _ext_clk_mux_index)
+		     _ext_clk_mux_index, NULL, 0)
+
+#define DEF_MOD_PARENT(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop, \
+			     _child_name, _child) \
+	DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit, \
+		     -1, _child_name, _child)
 
 /**
  * struct rzv2h_reset - Reset definitions
-- 
2.43.0

Re: [PATCH 2/4] clk: renesas: rzv2h: Add support for parent mod clocks

[Dan Carpenter]

Hi Biju,

kernel test robot noticed the following build warnings:

https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Biju/clk-renesas-rzv2h-Refactor-rzv2h_cpg_fixed_mod_status_clk_register/20250814-205111
base:   https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git renesas-clk
patch link:    https://lore.kernel.org/r/20250814124832.76266-3-biju.das.jz%40bp.renesas.com
patch subject: [PATCH 2/4] clk: renesas: rzv2h: Add support for parent mod clocks
config: hexagon-randconfig-r072-20250815 (https://download.01.org/0day-ci/archive/20250816/202508160958.ounSAlER-lkp@intel.com/config)
compiler: clang version 22.0.0git (https://github.com/llvm/llvm-project 93d24b6b7b148c47a2fa228a4ef31524fa1d9f3f)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Reported-by: Dan Carpenter <dan.carpenter@linaro.org>
| Closes: https://lore.kernel.org/r/202508160958.ounSAlER-lkp@intel.com/

New smatch warnings:
drivers/clk/renesas/rzv2h-cpg.c:875 rzv2h_cpg_register_mod_clk() warn: passing zero to 'PTR_ERR'

vim +/PTR_ERR +875 drivers/clk/renesas/rzv2h-cpg.c

dd22e56217495e Lad Prabhakar 2024-07-29  770  static void __init
dd22e56217495e Lad Prabhakar 2024-07-29  771  rzv2h_cpg_register_mod_clk(const struct rzv2h_mod_clk *mod,
dd22e56217495e Lad Prabhakar 2024-07-29  772  			   struct rzv2h_cpg_priv *priv)
dd22e56217495e Lad Prabhakar 2024-07-29  773  {
dd22e56217495e Lad Prabhakar 2024-07-29  774  	struct mod_clock *clock = NULL;
dd22e56217495e Lad Prabhakar 2024-07-29  775  	struct device *dev = priv->dev;
dd22e56217495e Lad Prabhakar 2024-07-29  776  	struct clk_init_data init;
dd22e56217495e Lad Prabhakar 2024-07-29  777  	struct clk *parent, *clk;
dd22e56217495e Lad Prabhakar 2024-07-29  778  	const char *parent_name;
dd22e56217495e Lad Prabhakar 2024-07-29  779  	unsigned int id;
dd22e56217495e Lad Prabhakar 2024-07-29  780  	int ret;
dd22e56217495e Lad Prabhakar 2024-07-29  781  
dd22e56217495e Lad Prabhakar 2024-07-29  782  	id = GET_MOD_CLK_ID(priv->num_core_clks, mod->on_index, mod->on_bit);
dd22e56217495e Lad Prabhakar 2024-07-29  783  	WARN_DEBUG(id >= priv->num_core_clks + priv->num_mod_clks);
dd22e56217495e Lad Prabhakar 2024-07-29  784  	WARN_DEBUG(mod->parent >= priv->num_core_clks + priv->num_mod_clks);
dd22e56217495e Lad Prabhakar 2024-07-29  785  	WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);
dd22e56217495e Lad Prabhakar 2024-07-29  786  
dd22e56217495e Lad Prabhakar 2024-07-29  787  	parent = priv->clks[mod->parent];
dd22e56217495e Lad Prabhakar 2024-07-29  788  	if (IS_ERR(parent)) {
dd22e56217495e Lad Prabhakar 2024-07-29  789  		clk = parent;
dd22e56217495e Lad Prabhakar 2024-07-29  790  		goto fail;
dd22e56217495e Lad Prabhakar 2024-07-29  791  	}
dd22e56217495e Lad Prabhakar 2024-07-29  792  
dd22e56217495e Lad Prabhakar 2024-07-29  793  	clock = devm_kzalloc(dev, sizeof(*clock), GFP_KERNEL);
dd22e56217495e Lad Prabhakar 2024-07-29  794  	if (!clock) {
dd22e56217495e Lad Prabhakar 2024-07-29  795  		clk = ERR_PTR(-ENOMEM);
dd22e56217495e Lad Prabhakar 2024-07-29  796  		goto fail;
dd22e56217495e Lad Prabhakar 2024-07-29  797  	}
dd22e56217495e Lad Prabhakar 2024-07-29  798  
dd22e56217495e Lad Prabhakar 2024-07-29  799  	init.name = mod->name;
dd22e56217495e Lad Prabhakar 2024-07-29  800  	init.ops = &rzv2h_mod_clock_ops;
dd22e56217495e Lad Prabhakar 2024-07-29  801  	init.flags = CLK_SET_RATE_PARENT;
dd22e56217495e Lad Prabhakar 2024-07-29  802  	if (mod->critical)
dd22e56217495e Lad Prabhakar 2024-07-29  803  		init.flags |= CLK_IS_CRITICAL;
dd22e56217495e Lad Prabhakar 2024-07-29  804  
dd22e56217495e Lad Prabhakar 2024-07-29  805  	parent_name = __clk_get_name(parent);
dd22e56217495e Lad Prabhakar 2024-07-29  806  	init.parent_names = &parent_name;
dd22e56217495e Lad Prabhakar 2024-07-29  807  	init.num_parents = 1;
dd22e56217495e Lad Prabhakar 2024-07-29  808  
dd22e56217495e Lad Prabhakar 2024-07-29  809  	clock->on_index = mod->on_index;
dd22e56217495e Lad Prabhakar 2024-07-29  810  	clock->on_bit = mod->on_bit;
dd22e56217495e Lad Prabhakar 2024-07-29  811  	clock->mon_index = mod->mon_index;
dd22e56217495e Lad Prabhakar 2024-07-29  812  	clock->mon_bit = mod->mon_bit;
03108a2614ecab Lad Prabhakar 2024-12-02  813  	clock->no_pm = mod->no_pm;
899e7ede4c19c6 Lad Prabhakar 2025-05-09  814  	clock->ext_clk_mux_index = mod->ext_clk_mux_index;
dd22e56217495e Lad Prabhakar 2024-07-29  815  	clock->priv = priv;
dd22e56217495e Lad Prabhakar 2024-07-29  816  	clock->hw.init = &init;
9b6e63a777ea5f Biju Das      2024-12-13  817  	clock->mstop_data = mod->mstop_data;
dd22e56217495e Lad Prabhakar 2024-07-29  818  
dd22e56217495e Lad Prabhakar 2024-07-29  819  	ret = devm_clk_hw_register(dev, &clock->hw);
dd22e56217495e Lad Prabhakar 2024-07-29  820  	if (ret) {
dd22e56217495e Lad Prabhakar 2024-07-29  821  		clk = ERR_PTR(ret);
dd22e56217495e Lad Prabhakar 2024-07-29  822  		goto fail;
dd22e56217495e Lad Prabhakar 2024-07-29  823  	}
dd22e56217495e Lad Prabhakar 2024-07-29  824  
dd22e56217495e Lad Prabhakar 2024-07-29  825  	priv->clks[id] = clock->hw.clk;
18610e6bf54faa Biju Das      2025-08-14  826  	if (mod->child_name) {
18610e6bf54faa Biju Das      2025-08-14  827  		WARN_DEBUG(mod->child >= priv->num_core_clks);
18610e6bf54faa Biju Das      2025-08-14  828  		WARN_DEBUG(PTR_ERR(priv->clks[mod->child]) != -ENOENT);
18610e6bf54faa Biju Das      2025-08-14  829  
18610e6bf54faa Biju Das      2025-08-14  830  		clk = rzv2h_cpg_mod_status_clk_register(priv, mod->child_name, mod->name, 1, 1,
18610e6bf54faa Biju Das      2025-08-14  831  							FIXED_MOD_CONF_PACK(mod->mon_index,
18610e6bf54faa Biju Das      2025-08-14  832  									    mod->mon_bit));
18610e6bf54faa Biju Das      2025-08-14  833  		if (IS_ERR_OR_NULL(clk))
18610e6bf54faa Biju Das      2025-08-14  834  			goto fail;

This isn't how IS_ERR_OR_NULL() is supposed to work...  :(  The NULL should
be treated like success, it shouldn't print an error message, unless it's
something like:

	WARN_ON_ONCE(!clk); // rzv2h_cpg_mod_status_clk_register() is buggy

I have written a blog about how how IS_ERR_OR_NULL() is supposed to work:
https://staticthinking.wordpress.com/2022/08/01/mixing-error-pointers-and-null/

18610e6bf54faa Biju Das      2025-08-14  835  		priv->clks[mod->child] = clk;
18610e6bf54faa Biju Das      2025-08-14  836  	}
dd22e56217495e Lad Prabhakar 2024-07-29  837  
9b6e63a777ea5f Biju Das      2024-12-13  838  	/*
9b6e63a777ea5f Biju Das      2024-12-13  839  	 * Ensure the module clocks and MSTOP bits are synchronized when they are
9b6e63a777ea5f Biju Das      2024-12-13  840  	 * turned ON by the bootloader. Enable MSTOP bits for module clocks that were
9b6e63a777ea5f Biju Das      2024-12-13  841  	 * turned ON in an earlier boot stage.
9b6e63a777ea5f Biju Das      2024-12-13  842  	 */
9b6e63a777ea5f Biju Das      2024-12-13  843  	if (clock->mstop_data != BUS_MSTOP_NONE &&
9b6e63a777ea5f Biju Das      2024-12-13  844  	    !mod->critical && rzv2h_mod_clock_is_enabled(&clock->hw)) {
9b6e63a777ea5f Biju Das      2024-12-13  845  		rzv2h_mod_clock_mstop_enable(priv, clock->mstop_data);
9b6e63a777ea5f Biju Das      2024-12-13  846  	} else if (clock->mstop_data != BUS_MSTOP_NONE && mod->critical) {
9b6e63a777ea5f Biju Das      2024-12-13  847  		unsigned long mstop_mask = FIELD_GET(BUS_MSTOP_BITS_MASK, clock->mstop_data);
9b6e63a777ea5f Biju Das      2024-12-13  848  		u16 mstop_index = FIELD_GET(BUS_MSTOP_IDX_MASK, clock->mstop_data);
69ac2acd209a15 Biju Das      2025-02-22  849  		atomic_t *mstop = &priv->mstop_count[mstop_index * 16];
9b6e63a777ea5f Biju Das      2024-12-13  850  		unsigned long flags;
9b6e63a777ea5f Biju Das      2024-12-13  851  		unsigned int i;
9b6e63a777ea5f Biju Das      2024-12-13  852  		u32 val = 0;
9b6e63a777ea5f Biju Das      2024-12-13  853  
9b6e63a777ea5f Biju Das      2024-12-13  854  		/*
9b6e63a777ea5f Biju Das      2024-12-13  855  		 * Critical clocks are turned ON immediately upon registration, and the
9b6e63a777ea5f Biju Das      2024-12-13  856  		 * MSTOP counter is updated through the rzv2h_mod_clock_enable() path.
9b6e63a777ea5f Biju Das      2024-12-13  857  		 * However, if the critical clocks were already turned ON by the initial
9b6e63a777ea5f Biju Das      2024-12-13  858  		 * bootloader, synchronize the atomic counter here and clear the MSTOP bit.
9b6e63a777ea5f Biju Das      2024-12-13  859  		 */
9b6e63a777ea5f Biju Das      2024-12-13  860  		spin_lock_irqsave(&priv->rmw_lock, flags);
9b6e63a777ea5f Biju Das      2024-12-13  861  		for_each_set_bit(i, &mstop_mask, 16) {
9b6e63a777ea5f Biju Das      2024-12-13  862  			if (atomic_read(&mstop[i]))
9b6e63a777ea5f Biju Das      2024-12-13  863  				continue;
9b6e63a777ea5f Biju Das      2024-12-13  864  			val |= BIT(i) << 16;
9b6e63a777ea5f Biju Das      2024-12-13  865  			atomic_inc(&mstop[i]);
9b6e63a777ea5f Biju Das      2024-12-13  866  		}
9b6e63a777ea5f Biju Das      2024-12-13  867  		if (val)
9b6e63a777ea5f Biju Das      2024-12-13  868  			writel(val, priv->base + CPG_BUS_MSTOP(mstop_index));
9b6e63a777ea5f Biju Das      2024-12-13  869  		spin_unlock_irqrestore(&priv->rmw_lock, flags);
9b6e63a777ea5f Biju Das      2024-12-13  870  	}
9b6e63a777ea5f Biju Das      2024-12-13  871  
dd22e56217495e Lad Prabhakar 2024-07-29  872  	return;
dd22e56217495e Lad Prabhakar 2024-07-29  873  
dd22e56217495e Lad Prabhakar 2024-07-29  874  fail:
dd22e56217495e Lad Prabhakar 2024-07-29 @875  	dev_err(dev, "Failed to register module clock %s: %ld\n",
dd22e56217495e Lad Prabhakar 2024-07-29  876  		mod->name, PTR_ERR(clk));
dd22e56217495e Lad Prabhakar 2024-07-29  877  }

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

RE: [PATCH 2/4] clk: renesas: rzv2h: Add support for parent mod clocks

[Biju Das]

Hi Dan Carpenter,

> -----Original Message-----
> From: Dan Carpenter <dan.carpenter@linaro.org>
> Sent: 16 August 2025 11:28
> Subject: Re: [PATCH 2/4] clk: renesas: rzv2h: Add support for parent mod clocks
> 
> Hi Biju,
> 
> kernel test robot noticed the following build warnings:
> 
> https://git-scm.com/docs/git-format-patch#_base_tree_information]
> 
> url:    https://github.com/intel-lab-lkp/linux/commits/Biju/clk-renesas-rzv2h-Refactor-
> rzv2h_cpg_fixed_mod_status_clk_register/20250814-205111
> base:   https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git renesas-clk
> patch link:    https://lore.kernel.org/r/20250814124832.76266-3-biju.das.jz%40bp.renesas.com
> patch subject: [PATCH 2/4] clk: renesas: rzv2h: Add support for parent mod clocks
> config: hexagon-randconfig-r072-20250815 (https://download.01.org/0day-
> ci/archive/20250816/202508160958.ounSAlER-lkp@intel.com/config)
> compiler: clang version 22.0.0git (https://github.com/llvm/llvm-project
> 93d24b6b7b148c47a2fa228a4ef31524fa1d9f3f)
> 
> If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit),
> kindly add following tags
> | Reported-by: kernel test robot <lkp@intel.com>
> | Reported-by: Dan Carpenter <dan.carpenter@linaro.org>
> | Closes: https://lore.kernel.org/r/202508160958.ounSAlER-lkp@intel.com/
> 
> New smatch warnings:
> drivers/clk/renesas/rzv2h-cpg.c:875 rzv2h_cpg_register_mod_clk() warn: passing zero to 'PTR_ERR'
> 
> vim +/PTR_ERR +875 drivers/clk/renesas/rzv2h-cpg.c
> 
> dd22e56217495e Lad Prabhakar 2024-07-29  770  static void __init dd22e56217495e Lad Prabhakar 2024-07-
> 29  771  rzv2h_cpg_register_mod_clk(const struct rzv2h_mod_clk *mod,
> dd22e56217495e Lad Prabhakar 2024-07-29  772  			   struct rzv2h_cpg_priv *priv)
> dd22e56217495e Lad Prabhakar 2024-07-29  773  {
> dd22e56217495e Lad Prabhakar 2024-07-29  774  	struct mod_clock *clock = NULL;
> dd22e56217495e Lad Prabhakar 2024-07-29  775  	struct device *dev = priv->dev;
> dd22e56217495e Lad Prabhakar 2024-07-29  776  	struct clk_init_data init;
> dd22e56217495e Lad Prabhakar 2024-07-29  777  	struct clk *parent, *clk;
> dd22e56217495e Lad Prabhakar 2024-07-29  778  	const char *parent_name;
> dd22e56217495e Lad Prabhakar 2024-07-29  779  	unsigned int id;
> dd22e56217495e Lad Prabhakar 2024-07-29  780  	int ret;
> dd22e56217495e Lad Prabhakar 2024-07-29  781
> dd22e56217495e Lad Prabhakar 2024-07-29  782  	id = GET_MOD_CLK_ID(priv->num_core_clks, mod-
> >on_index, mod->on_bit);
> dd22e56217495e Lad Prabhakar 2024-07-29  783  	WARN_DEBUG(id >= priv->num_core_clks + priv-
> >num_mod_clks);
> dd22e56217495e Lad Prabhakar 2024-07-29  784  	WARN_DEBUG(mod->parent >= priv->num_core_clks + priv-
> >num_mod_clks);
> dd22e56217495e Lad Prabhakar 2024-07-29  785  	WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);
> dd22e56217495e Lad Prabhakar 2024-07-29  786
> dd22e56217495e Lad Prabhakar 2024-07-29  787  	parent = priv->clks[mod->parent];
> dd22e56217495e Lad Prabhakar 2024-07-29  788  	if (IS_ERR(parent)) {
> dd22e56217495e Lad Prabhakar 2024-07-29  789  		clk = parent;
> dd22e56217495e Lad Prabhakar 2024-07-29  790  		goto fail;
> dd22e56217495e Lad Prabhakar 2024-07-29  791  	}
> dd22e56217495e Lad Prabhakar 2024-07-29  792
> dd22e56217495e Lad Prabhakar 2024-07-29  793  	clock = devm_kzalloc(dev, sizeof(*clock), GFP_KERNEL);
> dd22e56217495e Lad Prabhakar 2024-07-29  794  	if (!clock) {
> dd22e56217495e Lad Prabhakar 2024-07-29  795  		clk = ERR_PTR(-ENOMEM);
> dd22e56217495e Lad Prabhakar 2024-07-29  796  		goto fail;
> dd22e56217495e Lad Prabhakar 2024-07-29  797  	}
> dd22e56217495e Lad Prabhakar 2024-07-29  798
> dd22e56217495e Lad Prabhakar 2024-07-29  799  	init.name = mod->name;
> dd22e56217495e Lad Prabhakar 2024-07-29  800  	init.ops = &rzv2h_mod_clock_ops;
> dd22e56217495e Lad Prabhakar 2024-07-29  801  	init.flags = CLK_SET_RATE_PARENT;
> dd22e56217495e Lad Prabhakar 2024-07-29  802  	if (mod->critical)
> dd22e56217495e Lad Prabhakar 2024-07-29  803  		init.flags |= CLK_IS_CRITICAL;
> dd22e56217495e Lad Prabhakar 2024-07-29  804
> dd22e56217495e Lad Prabhakar 2024-07-29  805  	parent_name = __clk_get_name(parent);
> dd22e56217495e Lad Prabhakar 2024-07-29  806  	init.parent_names = &parent_name;
> dd22e56217495e Lad Prabhakar 2024-07-29  807  	init.num_parents = 1;
> dd22e56217495e Lad Prabhakar 2024-07-29  808
> dd22e56217495e Lad Prabhakar 2024-07-29  809  	clock->on_index = mod->on_index;
> dd22e56217495e Lad Prabhakar 2024-07-29  810  	clock->on_bit = mod->on_bit;
> dd22e56217495e Lad Prabhakar 2024-07-29  811  	clock->mon_index = mod->mon_index;
> dd22e56217495e Lad Prabhakar 2024-07-29  812  	clock->mon_bit = mod->mon_bit;
> 03108a2614ecab Lad Prabhakar 2024-12-02  813  	clock->no_pm = mod->no_pm;
> 899e7ede4c19c6 Lad Prabhakar 2025-05-09  814  	clock->ext_clk_mux_index = mod->ext_clk_mux_index;
> dd22e56217495e Lad Prabhakar 2024-07-29  815  	clock->priv = priv;
> dd22e56217495e Lad Prabhakar 2024-07-29  816  	clock->hw.init = &init;
> 9b6e63a777ea5f Biju Das      2024-12-13  817  	clock->mstop_data = mod->mstop_data;
> dd22e56217495e Lad Prabhakar 2024-07-29  818
> dd22e56217495e Lad Prabhakar 2024-07-29  819  	ret = devm_clk_hw_register(dev, &clock->hw);
> dd22e56217495e Lad Prabhakar 2024-07-29  820  	if (ret) {
> dd22e56217495e Lad Prabhakar 2024-07-29  821  		clk = ERR_PTR(ret);
> dd22e56217495e Lad Prabhakar 2024-07-29  822  		goto fail;
> dd22e56217495e Lad Prabhakar 2024-07-29  823  	}
> dd22e56217495e Lad Prabhakar 2024-07-29  824
> dd22e56217495e Lad Prabhakar 2024-07-29  825  	priv->clks[id] = clock->hw.clk;
> 18610e6bf54faa Biju Das      2025-08-14  826  	if (mod->child_name) {
> 18610e6bf54faa Biju Das      2025-08-14  827  		WARN_DEBUG(mod->child >= priv->num_core_clks);
> 18610e6bf54faa Biju Das      2025-08-14  828  		WARN_DEBUG(PTR_ERR(priv->clks[mod->child]) != -
> ENOENT);
> 18610e6bf54faa Biju Das      2025-08-14  829
> 18610e6bf54faa Biju Das      2025-08-14  830  		clk = rzv2h_cpg_mod_status_clk_register(priv,
> mod->child_name, mod->name, 1, 1,
> 18610e6bf54faa Biju Das      2025-08-14  831
> 	FIXED_MOD_CONF_PACK(mod->mon_index,
> 18610e6bf54faa Biju Das      2025-08-14  832
> mod->mon_bit));
> 18610e6bf54faa Biju Das      2025-08-14  833  		if (IS_ERR_OR_NULL(clk))
> 18610e6bf54faa Biju Das      2025-08-14  834  			goto fail;
> 
> This isn't how IS_ERR_OR_NULL() is supposed to work...  :(  The NULL should be treated like success, it
> shouldn't print an error message, unless it's something like:

OK.
> 
> 	WARN_ON_ONCE(!clk); // rzv2h_cpg_mod_status_clk_register() is buggy
> 
> I have written a blog about how how IS_ERR_OR_NULL() is supposed to work:
> https://staticthinking.wordpress.com/2022/08/01/mixing-error-pointers-and-null/

Thanks for the link. Will take care next time.

I would like to drop this patch as Geert provided some
feedback to remodel the clocks[1].

[1] https://lore.kernel.org/all/CAMuHMdXJBL_uJ=2v0aKJaSf45070yP=Z_kPe-9uSyE1P0QeiJQ@mail.gmail.com/

Cheers,
Biju

[PATCH 3/4] dt-bindings: clock: renesas,r9a09g047-cpg: Add GPT core clocks

[Biju]

From: Biju Das <biju.das.jz@bp.renesas.com>

Add definitions for GPT core clocks in the R9A09G047 CPG DT bindings
header file.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 include/dt-bindings/clock/renesas,r9a09g047-cpg.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/dt-bindings/clock/renesas,r9a09g047-cpg.h b/include/dt-bindings/clock/renesas,r9a09g047-cpg.h
index a27132f9a6c8..ac0f1ce3c752 100644
--- a/include/dt-bindings/clock/renesas,r9a09g047-cpg.h
+++ b/include/dt-bindings/clock/renesas,r9a09g047-cpg.h
@@ -20,5 +20,7 @@
 #define R9A09G047_SPI_CLK_SPI			9
 #define R9A09G047_GBETH_0_CLK_PTP_REF_I		10
 #define R9A09G047_GBETH_1_CLK_PTP_REF_I		11
+#define R9A09G047_GPT_0_CLKS_GPT		12
+#define R9A09G047_GPT_1_CLKS_GPT		13
 
 #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__ */
-- 
2.43.0

Re: [PATCH 3/4] dt-bindings: clock: renesas,r9a09g047-cpg: Add GPT core clocks

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 309 bytes --]

On Thu, Aug 14, 2025 at 01:48:26PM +0100, Biju wrote:
> From: Biju Das <biju.das.jz@bp.renesas.com>
> 
> Add definitions for GPT core clocks in the R9A09G047 CPG DT bindings
> header file.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

Acked-by: Conor Dooley <conor.dooley@microchip.com>

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

RE: [PATCH 3/4] dt-bindings: clock: renesas,r9a09g047-cpg: Add GPT core clocks

[Biju Das]

Hi Conor,

> -----Original Message-----
> From: Conor Dooley <conor@kernel.org>
> Sent: 14 August 2025 20:49
> Subject: Re: [PATCH 3/4] dt-bindings: clock: renesas,r9a09g047-cpg: Add GPT core clocks
> 
> On Thu, Aug 14, 2025 at 01:48:26PM +0100, Biju wrote:
> > From: Biju Das <biju.das.jz@bp.renesas.com>
> >
> > Add definitions for GPT core clocks in the R9A09G047 CPG DT bindings
> > header file.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> 
> Acked-by: Conor Dooley <conor.dooley@microchip.com>

I am dropping this patch based on [1]
[1] https://lore.kernel.org/all/TY3PR01MB113467CB44FFF5F65038153EA8633A@TY3PR01MB11346.jpnprd01.prod.outlook.com/

Cheers,
Biju

[PATCH 4/4] clk: renesas: r9a09g047: Add GPT clocks and resets

[Biju]

From: Biju Das <biju.das.jz@bp.renesas.com>

Add clock and reset entries for the Renesas RZ/G3E GPT{0,1} IPs.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/clk/renesas/r9a09g047-cpg.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/renesas/r9a09g047-cpg.c b/drivers/clk/renesas/r9a09g047-cpg.c
index 4e8881e0006b..583a2ca116fd 100644
--- a/drivers/clk/renesas/r9a09g047-cpg.c
+++ b/drivers/clk/renesas/r9a09g047-cpg.c
@@ -16,7 +16,7 @@
 
 enum clk_ids {
 	/* Core Clock Outputs exported to DT */
-	LAST_DT_CORE_CLK = R9A09G047_GBETH_1_CLK_PTP_REF_I,
+	LAST_DT_CORE_CLK = R9A09G047_GPT_1_CLKS_GPT,
 
 	/* External Input Clocks */
 	CLK_AUDIO_EXTAL,
@@ -198,6 +198,10 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
 						BUS_MSTOP_NONE),
 	DEF_MOD_CRITICAL("gic_0_gicclk",	CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19,
 						BUS_MSTOP(3, BIT(5))),
+	DEF_MOD_PARENT("gpt_0_pclk_sfr",	CLK_PLLCLN_DIV8, 3, 1, 1, 17,
+						BUS_MSTOP(6, BIT(11)), "gpt_0_clks_gpt", R9A09G047_GPT_0_CLKS_GPT),
+	DEF_MOD_PARENT("gpt_1_pclk_sfr",	CLK_PLLCLN_DIV8, 3, 2, 1, 18,
+						BUS_MSTOP(6, BIT(12)), "gpt_1_clks_gpt", R9A09G047_GPT_1_CLKS_GPT),
 	DEF_MOD("wdt_1_clkp",			CLK_PLLCLN_DIV16, 4, 13, 2, 13,
 						BUS_MSTOP(1, BIT(0))),
 	DEF_MOD("wdt_1_clk_loco",		CLK_QEXTAL, 4, 14, 2, 14,
@@ -322,6 +326,10 @@ static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
 	DEF_RST(3, 6, 1, 7),		/* ICU_0_PRESETN_I */
 	DEF_RST(3, 8, 1, 9),		/* GIC_0_GICRESET_N */
 	DEF_RST(3, 9, 1, 10),		/* GIC_0_DBG_GICRESET_N */
+	DEF_RST(5, 9, 2, 10),		/* GPT_0_RST_P_REG */
+	DEF_RST(5, 10, 2, 11),		/* GPT_0_RST_S_REG */
+	DEF_RST(5, 11, 2, 12),		/* GPT_1_RST_P_REG */
+	DEF_RST(5, 12, 2, 13),		/* GPT_1_RST_S_REG */
 	DEF_RST(7, 6, 3, 7),		/* WDT_1_RESET */
 	DEF_RST(7, 7, 3, 8),		/* WDT_2_RESET */
 	DEF_RST(7, 8, 3, 9),		/* WDT_3_RESET */
-- 
2.43.0

Re: [PATCH 0/4] Add RZ/G3E GPT clocks and resets

[Geert Uytterhoeven]

Hi Biju,

On Thu, 14 Aug 2025 at 14:48, Biju <biju.das.au@gmail.com> wrote:
> From: Biju Das <biju.das.jz@bp.renesas.com>
>
> The RZ/G3E GPT IP has multiple clocks and resets. It has bus and core
> clocks. The bus clock is module clock and core clock is sourced from
> the bus clock. So add support for module clock as parent reusing the
> existing rzv2h_cpg_fixed_mod_status_clk_register().

Thanks for your series!

> Biju Das (4):
>   clk: renesas: rzv2h: Refactor
>     rzv2h_cpg_fixed_mod_status_clk_register()
>   clk: renesas: rzv2h: Add support for parent mod clocks
>   dt-bindings: clock: renesas,r9a09g047-cpg: Add GPT core clocks
>   clk: renesas: r9a09g047: Add GPT clocks and resets

I think you are overcomplicating: according to the clock system diagram
and clock list sheets, gpt_[01]_pclk_sfr and gpt_[01]_clks_gpt_sfr
are really the same clocks (the same is true for rsci_[0-9]_pclk and
rsci_[0-9]_pclk_sfr).
So you can just describe gpt_[01]_pclk_sfr as normal module clocks,
and use them for both the core and bus blocks in DT, e.g.

    clocks = <&cpg CPG_MOD 0x31>, <&cpg CPG_MOD 0x31>;
    clock-names = "core", "bus";

Do you agree?

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH 0/4] Add RZ/G3E GPT clocks and resets

[Biju Das]

Hi Geert,

Thanks for the feedback.

> -----Original Message-----
> From: Geert Uytterhoeven <geert@linux-m68k.org>
> Sent: 19 August 2025 16:11
> Subject: Re: [PATCH 0/4] Add RZ/G3E GPT clocks and resets
> 
> Hi Biju,
> 
> On Thu, 14 Aug 2025 at 14:48, Biju <biju.das.au@gmail.com> wrote:
> > From: Biju Das <biju.das.jz@bp.renesas.com>
> >
> > The RZ/G3E GPT IP has multiple clocks and resets. It has bus and core
> > clocks. The bus clock is module clock and core clock is sourced from
> > the bus clock. So add support for module clock as parent reusing the
> > existing rzv2h_cpg_fixed_mod_status_clk_register().
> 
> Thanks for your series!
> 
> > Biju Das (4):
> >   clk: renesas: rzv2h: Refactor
> >     rzv2h_cpg_fixed_mod_status_clk_register()
> >   clk: renesas: rzv2h: Add support for parent mod clocks
> >   dt-bindings: clock: renesas,r9a09g047-cpg: Add GPT core clocks
> >   clk: renesas: r9a09g047: Add GPT clocks and resets
> 
> I think you are overcomplicating: according to the clock system diagram and clock list sheets,
> gpt_[01]_pclk_sfr and gpt_[01]_clks_gpt_sfr are really the same clocks (the same is true for rsci_[0-
> 9]_pclk and rsci_[0-9]_pclk_sfr).

Thanks for correcting me. I got confused with CGC=GPT_0_pclk_sfr for the core clock
that made me to complicate the clks.

> So you can just describe gpt_[01]_pclk_sfr as normal module clocks, and use them for both the core and
> bus blocks in DT, e.g.
> 
>     clocks = <&cpg CPG_MOD 0x31>, <&cpg CPG_MOD 0x31>;
>     clock-names = "core", "bus";
> 
> Do you agree?

Yes, I agree.

Cheers,
Biju

Re: [PATCH 0/4] Add RZ/G3E GPT clocks and resets

[Geert Uytterhoeven]

On Tue, 19 Aug 2025 at 17:10, Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> I think you are overcomplicating: according to the clock system diagram
> and clock list sheets, gpt_[01]_pclk_sfr and gpt_[01]_clks_gpt_sfr

s/gpt_[01]_clks_gpt_sfr/gpt_[01]_clks_gpt/

> are really the same clocks (the same is true for rsci_[0-9]_pclk and
> rsci_[0-9]_pclk_sfr).

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds