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[209.85.222.42]) by smtp.gmail.com with ESMTPSA id 71dfb90a1353d-53323b0f091sm1017153e0c.0.2025.07.01.01.06.01 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 01 Jul 2025 01:06:01 -0700 (PDT) Received: by mail-ua1-f42.google.com with SMTP id a1e0cc1a2514c-87f2170921dso635112241.0; Tue, 01 Jul 2025 01:06:01 -0700 (PDT) X-Forwarded-Encrypted: i=1; AJvYcCUZgmvX7WL7FpiNjQKW4B28tg4kyIdoIsenjcbHkQEH32IFUyvwM4HjShQaYbcPDZIfY+5EnHQu@vger.kernel.org, AJvYcCUm0bXwH8/6RWCsN8ZDWsgwV5D4c2Mb7r149TP+H2hcR/zfzMzzHx6swkdkXhOzhWw/ZsbNdEqQfBysKOwv@vger.kernel.org, AJvYcCUy3WJDYSbCZfzB1CxWWdsIPpURi1joXouN7UdV/ATw6PI9VWY8t2c0KMOohSeL1DCJSkCZgGF2XnPk9ycO+zZZzD0=@vger.kernel.org, AJvYcCXxoQ9EhyHGwAVrOYlkMEUPtcVfIn+blN027k5OSvM33schn/Kz25ivjOZDqN8z3uoBz/Xra9QZdfzI@vger.kernel.org X-Received: by 2002:a05:6102:5717:b0:4e9:c773:dca1 with SMTP id ada2fe7eead31-4ee4f6d96fbmr11242699137.11.1751357161130; Tue, 01 Jul 2025 01:06:01 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20250611061609.15527-1-john.madieu.xa@bp.renesas.com> <20250611061609.15527-2-john.madieu.xa@bp.renesas.com> In-Reply-To: From: Geert Uytterhoeven Date: Tue, 1 Jul 2025 10:05:49 +0200 X-Gmail-Original-Message-ID: X-Gm-Features: Ac12FXyTtjI4YTwpovffxojy8Q1Ejihuqc3wkPKs28S37LOjQ2ir27DL4UhK71w Message-ID: Subject: Re: [PATCH v2 1/3] clk: renesas: r9a09g047: Add clock and reset signals for the GBETH IPs To: John Madieu Cc: "andrew+netdev@lunn.ch" , "conor+dt@kernel.org" , "davem@davemloft.net" , "edumazet@google.com" , "krzk+dt@kernel.org" , "kuba@kernel.org" , "pabeni@redhat.com" , Prabhakar Mahadev Lad , "robh@kernel.org" , Biju Das , "Lad, Prabhakar" , "devicetree@vger.kernel.org" , "john.madieu@gmail.com" , "linux-kernel@vger.kernel.org" , "linux-renesas-soc@vger.kernel.org" , "magnus.damm@gmail.com" , "netdev@vger.kernel.org" Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi John, On Mon, 30 Jun 2025 at 18:23, John Madieu w= rote: > > From: Geert Uytterhoeven > > On Thu, 19 Jun 2025 at 10:22, Lad, Prabhakar > > wrote: > > > On Thu, Jun 19, 2025 at 5:34=E2=80=AFAM John Madieu > > > wrote: > > > > > From: Geert Uytterhoeven On Wed, 18 Jun > > > > > 2025 at 12:04, John Madieu > > > > > wrote: > > > > > > > From: Geert Uytterhoeven On Wed, 11 Ju= n > > > > > > > 2025 at 11:02, John Madieu > > > > > > > wrote: > > > > > > > > Add clock and reset entries for the Gigabit Ethernet > > > > > > > > Interfaces (GBETH > > > > > > > > 0-1) IPs found on the RZ/G3E SoC. This includes various > > > > > > > > PLLs, dividers, and mux clocks needed by these two GBETH IP= s. > > > > > > > > > > > > > > > > Reviewed-by: Biju Das > > > > > > > > Tested-by: Biju Das > > > > > > > > Signed-off-by: John Madieu > > > > > > > > > > > > > > Thanks for your patch! > > > > > > > > > > > > > > > --- a/drivers/clk/renesas/r9a09g047-cpg.c > > > > > > > > +++ b/drivers/clk/renesas/r9a09g047-cpg.c > > > > > > "The clock gating cells require source clocks to operate correctly. I= f > > > the source clocks are stopped, these registers cannot be used." > > > > Has this been sorted out yet? I see no change or mention of it in v3. > > Yes, it has been sorted out. I mean they operated properly after > all the tests, even after S2R/wakeup test. > > While at it, even with OEN patches applied, I could not reproduce > the issue known to V2H. That's why I've asked if you'd prefer > DEF_MOD_EXTERNAL instead of DEF_MOD (which does not work on V2H) > for consistency with RZ/V2H, I can do that as well. As DEF_MOD_MUX_EXTERNAL() better matches the undelying hardware, I prefer that. Thanks! Gr{oetje,eeting}s, Geert --=20 Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k= .org In personal conversations with technical people, I call myself a hacker. Bu= t when I'm talking to journalists I just say "programmer" or something like t= hat. -- Linus Torvalds