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AJvYcCUdw1u9sGsb342wkx+EYepAr8RvbhQ1qLNB5S74m2IGy5xhbkyJSfqO/I+2+WTkFuDu7QM=@vger.kernel.org X-Gm-Message-State: AOJu0YwWkRTeQoR82ULK0wy+j6HPwJoAgi738FdKkHcve0EQczOEsedP KyYtGc8heSVHUan1KLFRNsjoZ35LioL8jCVXJfrM+u556YJhoZ734CiR05NCe19NwocJLJJEtJ9 n/7WmBMQS6ild4+15s5MU3UM34zD+l5WwIvSB X-Gm-Gg: ASbGncvfHwI0gBVNhZiM0WxF2ak7BZMT7uqnG3ZXDmZxOGuB0rRYeTZeYlL9ff3Oamh rY9xtoeqxMpqaXejNtcqo/Yca/LV6SgLngjU5hS617Y9FyRCf8VYbzrAAPeDCj+Uml/2duigApk rU5s8uVe1b3HAfndpDQt3d59ERU3fVBA0tWVFPFDeyoqgq/hcPeu+yXYhnV3GZyWDhek4s7qsSm hhP X-Google-Smtp-Source: AGHT+IGxWiZyFqVw9AjSaPi2Sc23P03HcxDfZWTEN4Fqh0PO26H/7Rb+SssHnNAUtj1iD6VvHNzSQ5JDeZ9ZQpeQmaE= X-Received: by 2002:a17:90b:5385:b0:312:e51c:af67 with SMTP id 98e67ed59e1d1-31c9f3ef43cmr20305386a91.1.1752987404676; Sat, 19 Jul 2025 21:56:44 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20250709033242.267892-1-Neeraj.Upadhyay@amd.com> <20250709033242.267892-32-Neeraj.Upadhyay@amd.com> In-Reply-To: <20250709033242.267892-32-Neeraj.Upadhyay@amd.com> From: Tianyu Lan Date: Sun, 20 Jul 2025 12:56:08 +0800 X-Gm-Features: Ac12FXxbBA4rbWTateJiA4BA_Ri5AI2fUNxGPr5R3jLnVzXFRH4t9QirRzJDtBY Message-ID: Subject: Re: [RFC PATCH v8 31/35] x86/apic: Handle EOI writes for Secure AVIC guests To: Neeraj Upadhyay Cc: linux-kernel@vger.kernel.org, bp@alien8.de, tglx@linutronix.de, mingo@redhat.com, dave.hansen@linux.intel.com, Thomas.Lendacky@amd.com, nikunj@amd.com, Santosh.Shukla@amd.com, Vasant.Hegde@amd.com, Suravee.Suthikulpanit@amd.com, David.Kaplan@amd.com, x86@kernel.org, hpa@zytor.com, peterz@infradead.org, seanjc@google.com, pbonzini@redhat.com, kvm@vger.kernel.org, kirill.shutemov@linux.intel.com, huibo.wang@amd.com, naveen.rao@amd.com, kai.huang@intel.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Wed, Jul 9, 2025 at 11:44=E2=80=AFAM Neeraj Upadhyay wrote: > > Secure AVIC accelerates guest's EOI msr writes for edge-triggered > interrupts. > > For level-triggered interrupts, EOI msr writes trigger VC exception > with SVM_EXIT_AVIC_UNACCELERATED_ACCESS error code. To complete EOI > handling, the VC exception handler would need to trigger a GHCB protocol > MSR write event to notify the hypervisor about completion of the > level-triggered interrupt. Hypervisor notification is required for > cases like emulated IOAPIC, to complete and clear interrupt in the > IOAPIC's interrupt state. > > However, VC exception handling adds extra performance overhead for > APIC register writes. In addition, for Secure AVIC, some unaccelerated > APIC register msr writes are trapped, whereas others are faulted. This > results in additional complexity in VC exception handling for unacclerate= d > APIC msr accesses. So, directly do a GHCB protocol based APIC EOI msr wri= te > from apic->eoi() callback for level-triggered interrupts. > > Use wrmsr for edge-triggered interrupts, so that hardware re-evaluates > any pending interrupt which can be delivered to guest vCPU. For level- > triggered interrupts, re-evaluation happens on return from VMGEXIT > corresponding to the GHCB event for APIC EOI msr write. > > Signed-off-by: Neeraj Upadhyay > --- > Changes since v7: > - No change. Reviewed-by: Tianyu Lan --=20 Thanks Tianyu Lan