From mboxrd@z Thu Jan 1 00:00:00 1970 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753633AbeABPDH (ORCPT + 1 other); Tue, 2 Jan 2018 10:03:07 -0500 Received: from mail-ot0-f196.google.com ([74.125.82.196]:46773 "EHLO mail-ot0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753594AbeABPDF (ORCPT ); Tue, 2 Jan 2018 10:03:05 -0500 X-Google-Smtp-Source: ACJfBovp2lwwu3FpqVF0NS0XKnHtx7d9rz2C3SCg7u9YioLKzja5VqI4cpc2CYD28DUjOKciQCFmML0/PeSoro+4yW8= MIME-Version: 1.0 In-Reply-To: <1514912859-17691-1-git-send-email-Anson.Huang@nxp.com> References: <1514912859-17691-1-git-send-email-Anson.Huang@nxp.com> From: Fabio Estevam Date: Tue, 2 Jan 2018 13:03:03 -0200 Message-ID: Subject: Re: [PATCH 1/2] ARM: dts: imx6ul: add 696MHz operating point To: Anson Huang Cc: "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , linux-pm@vger.kernel.org, linux-kernel , Mark Rutland , Dong Aisheng , Ping Bai , viresh kumar , rjw@rjwysocki.net, Russell King - ARM Linux , Rob Herring , Sascha Hauer , Fabio Estevam , Shawn Guo Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Return-Path: Hi Anson, On Tue, Jan 2, 2018 at 3:07 PM, Anson Huang wrote: > Add 696MHz operating point according to datasheet > (Rev. 0, 12/2015). There is a newer version from 05/2017: https://www.nxp.com/docs/en/data-sheet/IMX6ULAEC.pdf > > Signed-off-by: Anson Huang > --- > arch/arm/boot/dts/imx6ul.dtsi | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi > index e0b4a46..86b3251 100644 > --- a/arch/arm/boot/dts/imx6ul.dtsi > +++ b/arch/arm/boot/dts/imx6ul.dtsi > @@ -68,12 +68,14 @@ > clock-latency = <61036>; /* two CLK32 periods */ > operating-points = < > /* kHz uV */ > + 696000 1275000 > 528000 1175000 > 396000 1025000 > 198000 950000 > >; > fsl,soc-operating-points = < > /* KHz uV */ > + 696000 1275000 Why 1.275V? According to the datasheet, the minimum value for VDD_SOC_CAP is 1.15V for all frequencies. Adding 25mV of margin leads to 1.175V.