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AJvYcCVHlphXLzMMFuAIvdCL4fVxYcUGxEoeN1VjIal3E0DUacDPk4EbmPYst9w5lXo6+t1/6HWmlzmBzx1mFaY=@vger.kernel.org X-Gm-Message-State: AOJu0Yze/ZuQi31PGJvPf9cg0pUrLedx1Y3YdqRzTvR1vGI4OIyKoHWN 2hYfKH2pa12gd7a0P/qCbCrCaK+nzPhqIXeIg+X7TmAl935byxJxEywMjrWTX7o5nogGyJiYfm7 J7k/hCbSUGxz3bsE4aI9VGE8+MuRdwDdBRMujWTMAPg== X-Gm-Gg: ASbGncvZwnC+U3RtQY/z0Pb8iKJZKDngx7vZ7dwbUc8OQyiaC/mhNWxcGzZa0sJ/4BR xLU/osbyeQV2CvM0ndoj+5t1JRdjdNcJLXuNSEr4EeH64jmLEXPIK9NfNzBacSrnrN0yKLhd2yy jv6/ptJjAXD/qT1PKelcDhDApYve/UbTcHQQ1NZJp442KU X-Google-Smtp-Source: AGHT+IH0AH5eQCmkoaKuxJOOgz4lFGdC1+XDKcfPC3cVk26SzauKoptzIDMdTxuXWb+pjp6Y/soe1VeW59yNxFQhyjU= X-Received: by 2002:a05:6902:1a49:b0:e7d:a4a7:439b with SMTP id 3f1490d57ef6-e822ad08e62mr28105508276.48.1750341940771; Thu, 19 Jun 2025 07:05:40 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20250618-apr_14_for_sending-v5-0-27ed33ea5c6f@samsung.com> <20250618-apr_14_for_sending-v5-3-27ed33ea5c6f@samsung.com> In-Reply-To: From: Ulf Hansson Date: Thu, 19 Jun 2025 16:05:03 +0200 X-Gm-Features: AX0GCFv2RIICzft_XZewOUAZZhSSWv8Je60KaQi8kC_SyLtOZnxRamWoHqyfp3U Message-ID: Subject: Re: [PATCH v5 3/8] pmdomain: thead: Instantiate GPU power sequencer via auxiliary bus To: Bartosz Golaszewski Cc: Michal Wilczynski , Drew Fustini , Guo Ren , Fu Wei , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Frank Binns , Matt Coster , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Marek Szyprowski , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, dri-devel@lists.freedesktop.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Thu, 19 Jun 2025 at 14:31, Bartosz Golaszewski wrote: > > On Thu, Jun 19, 2025 at 12:25=E2=80=AFPM Ulf Hansson wrote: > > > > On Wed, 18 Jun 2025 at 12:22, Michal Wilczynski > > wrote: > > > > > > In order to support the complex power sequencing required by the TH15= 20 > > > GPU, the AON power domain driver must be responsible for initiating t= he > > > corresponding sequencer driver. This functionality is specific to > > > platforms where the GPU power sequencing hardware is controlled by th= e > > > AON block. > > > > > > Extend the AON power domain driver to check for the presence of the > > > "gpu-clkgen" reset in its own device tree node. > > > > > > If the property is found, create and register a new auxiliary device. > > > This device acts as a proxy that allows the dedicated `pwrseq-thead-g= pu` > > > auxiliary driver to bind and take control of the sequencing logic. > > > > > > Signed-off-by: Michal Wilczynski > > > > Reviewed-by: Ulf Hansson > > > > It looks like there is another re-spin needed, but thinking of the > > merge-strategy I could potentially take patch1->patch3 via my pmdomain > > tree, as it seems reasonable to keep those changes together. Unless > > Bartosz sees any problem with that, of course. > > > > I have another change planned for the pwrseq API for this cycle. > Nothing major but it still will require patch 1/8 to be in my tree so > if you don't mind, I'll take it hrough the pwrseq tree and provide you > an immutable tag to pull before you apply the rest? Right, that works perfectly fine too. I will wait for you to give me the branch then, before applying anything. Kind regards Uffe