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Wed, 27 Aug 2025 03:45:39 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20250819121631.84280-1-clamor95@gmail.com> <1909286.atdPhlSkOF@senjougahara> <76B1EB6D-B149-43C2-AA56-A15C9DCCA3AF@gmail.com> <14287352.RDIVbhacDa@senjougahara> In-Reply-To: <14287352.RDIVbhacDa@senjougahara> From: Svyatoslav Ryhel Date: Wed, 27 Aug 2025 13:45:28 +0300 X-Gm-Features: Ac12FXzDJMFwSyCznjWDvhfBWLuEGGUDton2Z3d8Y-Yt9F2wgfNpu5x2X_82XmI Message-ID: Subject: Re: [PATCH v1 01/19] clk: tegra: init CSUS clock for Tegra20 and Tegra30 To: Mikko Perttunen Cc: Thierry Reding , Thierry Reding , Jonathan Hunter , Sowjanya Komatineni , Luca Ceresoli , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Peter De Schrijver , Prashant Gaikwad , Michael Turquette , Stephen Boyd , Mauro Carvalho Chehab , Greg Kroah-Hartman , Dmitry Osipenko , Charan Pedumuru , linux-media@vger.kernel.org, linux-tegra@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-staging@lists.linux.dev Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable =D1=81=D1=80, 27 =D1=81=D0=B5=D1=80=D0=BF. 2025=E2=80=AF=D1=80. =D0=BE 13:3= 6 Mikko Perttunen =D0=BF=D0=B8=D1=88=D0=B5: > > On Wednesday, August 27, 2025 1:32=E2=80=AFPM Svyatoslav wrote: > > 27 =D1=81=D0=B5=D1=80=D0=BF=D0=BD=D1=8F 2025=E2=80=AF=D1=80. 07:09:45 G= MT+03:00, Mikko Perttunen > =D0=BF=D0=B8=D1=88=D0=B5: > > >On Tuesday, August 19, 2025 9:16=E2=80=AFPM Svyatoslav Ryhel wrote: > > >> CSUS clock is required to be enabled on camera device configuration = or > > >> else camera module refuses to initiate properly. > > >> > > >> Signed-off-by: Svyatoslav Ryhel > > >> --- > > >> > > >> drivers/clk/tegra/clk-tegra20.c | 1 + > > >> drivers/clk/tegra/clk-tegra30.c | 1 + > > >> 2 files changed, 2 insertions(+) > > >> > > >> diff --git a/drivers/clk/tegra/clk-tegra20.c > > >> b/drivers/clk/tegra/clk-tegra20.c index 551ef0cf0c9a..42f8150c6110 1= 00644 > > >> --- a/drivers/clk/tegra/clk-tegra20.c > > >> +++ b/drivers/clk/tegra/clk-tegra20.c > > >> @@ -1043,6 +1043,7 @@ static struct tegra_clk_init_table init_table[= ] =3D { > > >> > > >> { TEGRA20_CLK_GR3D, TEGRA20_CLK_PLL_C, 300000000, 0 }, > > >> { TEGRA20_CLK_VDE, TEGRA20_CLK_PLL_C, 300000000, 0 }, > > >> { TEGRA20_CLK_PWM, TEGRA20_CLK_PLL_P, 48000000, 0 }, > > >> > > >> + { TEGRA20_CLK_CSUS, TEGRA20_CLK_CLK_MAX, 6000000, 1 }, > > >> > > >> /* must be the last entry */ > > >> { TEGRA20_CLK_CLK_MAX, TEGRA20_CLK_CLK_MAX, 0, 0 }, > > >> > > >> }; > > >> > > >> diff --git a/drivers/clk/tegra/clk-tegra30.c > > >> b/drivers/clk/tegra/clk-tegra30.c index 82a8cb9545eb..70e85e2949e0 1= 00644 > > >> --- a/drivers/clk/tegra/clk-tegra30.c > > >> +++ b/drivers/clk/tegra/clk-tegra30.c > > >> @@ -1237,6 +1237,7 @@ static struct tegra_clk_init_table init_table[= ] =3D { > > >> > > >> { TEGRA30_CLK_HDA, TEGRA30_CLK_PLL_P, 102000000, 0 }, > > >> { TEGRA30_CLK_HDA2CODEC_2X, TEGRA30_CLK_PLL_P, 48000000, 0 }, > > >> { TEGRA30_CLK_PWM, TEGRA30_CLK_PLL_P, 48000000, 0 }, > > >> > > >> + { TEGRA30_CLK_CSUS, TEGRA30_CLK_CLK_MAX, 6000000, 1 }, > > >> > > >> /* must be the last entry */ > > >> { TEGRA30_CLK_CLK_MAX, TEGRA30_CLK_CLK_MAX, 0, 0 }, > > >> > > >> }; > > > > > >I looked into what this clock does and it seems to be a gate for the C= SUS > > >pin, which provides an output clock for camera sensors (VI MCLK). Defa= ult > > >source seems to be PLLC_OUT1. It would be good to note that on the com= mit > > >message, as I can't find any documentation about the CSUS clock elsewh= ere. > > > > > >What is the 6MHz rate based on? > > > > 6mhz is the statistic value which I was not able to alter while testing= . I > > have tried 12mhz and 24mhz too but it remained 6mhz, so I left it 6mhz. > > >Since this seems to be a clock consumed by the sensor, it seems to me = that > > >rather than making it always on, we could point to it in the sensor's > > >device tree entry. > > > > Sensor device tree uses vi_sensor as clocks source and sensor drivers d= on't > > support multiple linked clocks. > > AIUI vi_sensor is an internal clock so the sensor cannot be receiving it > directly. Perhaps the sensor is actually connected to csus, and the reaso= n we > need to enable it is to allow the vi_sensor clock to pass through the csu= s > gate? > > That leaves the question of why the csus pad would be muxed to vi_sensor = by > default, but perhaps there's an explanation for that. > >From downstream T30 sources csus and vi_sensor are always called in pair (6MHz csus and 24MHz for vi_sensor), naturally I assumed that latter is used as camera reference clock since most sensors has reference clock around 24 MHz > > >Cheers, > > >Mikko > > > >