From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753117AbbAEHzi (ORCPT ); Mon, 5 Jan 2015 02:55:38 -0500 Received: from mail-bn1on0114.outbound.protection.outlook.com ([157.56.110.114]:44608 "EHLO na01-bn1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751087AbbAEHzg convert rfc822-to-8bit (ORCPT ); Mon, 5 Jan 2015 02:55:36 -0500 X-WSS-ID: 0NHP20H-08-L4B-02 X-M-MSG: From: "Suthikulpanit, Suravee" To: Hanjun Guo , Catalin Marinas , "Rafael J. Wysocki" , "Olof Johansson" , Arnd Bergmann , Mark Rutland , Grant Likely , Will Deacon CC: Lorenzo Pieralisi , Graeme Gregory , Sudeep Holla , Jon Masters , Jason Cooper , Marc Zyngier , Bjorn Helgaas , Mark Brown , Rob Herring , Robert Richter , Randy Dunlap , "Charles.Garcia-Tobin@arm.com" , "phoenix.liyi@huawei.com" , Timur Tabi , "linux-acpi@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "linaro-acpi@lists.linaro.org" Subject: Re: [PATCH v6 14/17] ARM64 / ACPI: Parse GTDT to initialize arch timer Thread-Topic: [PATCH v6 14/17] ARM64 / ACPI: Parse GTDT to initialize arch timer Thread-Index: AQHQKA0xYxhebyGctk2vnXL1SlXTO5yxGRGA Date: Mon, 5 Jan 2015 07:55:30 +0000 Message-ID: In-Reply-To: <1420368918-5086-15-git-send-email-hanjun.guo@linaro.org> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: user-agent: Microsoft-MacOutlook/14.3.0.121105 x-originating-ip: [10.177.96.13] Content-Type: text/plain; charset="us-ascii" Content-ID: <49B6EEC1D45AFD488824FE419745F1DC@amd.com> Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 X-EOPAttributedMessage: 0 Authentication-Results: spf=none (sender IP is 165.204.84.222) smtp.mailfrom=Suravee.Suthikulpanit@amd.com; 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X-OriginatorOrg: amd4.onmicrosoft.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jan 2015 07:55:32.5165 (UTC) X-MS-Exchange-CrossTenant-Id: fde4dada-be84-483f-92cc-e026cbee8e96 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=fde4dada-be84-483f-92cc-e026cbee8e96;Ip=[165.204.84.222] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN1PR02MB197 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 1/4/15, 04:55, "Hanjun Guo" wrote: >Using the information presented by GTDT to initialize the arch >timer (not memory-mapped). > >Originally-by: Amit Daniel Kachhap >Tested-by: Suravee Suthikulpanit >Signed-off-by: Hanjun Guo >--- > arch/arm64/kernel/time.c | 7 ++ > drivers/clocksource/arm_arch_timer.c | 132 >++++++++++++++++++++++++++++------- > include/linux/clocksource.h | 6 ++ > 3 files changed, 118 insertions(+), 27 deletions(-) > >diff --git a/arch/arm64/kernel/time.c b/arch/arm64/kernel/time.c >index 1a7125c..42f9195 100644 >--- a/arch/arm64/kernel/time.c >+++ b/arch/arm64/kernel/time.c >@@ -35,6 +35,7 @@ > #include > #include > #include >+#include > > #include > >@@ -72,6 +73,12 @@ void __init time_init(void) > > tick_setup_hrtimer_broadcast(); > >+ /* >+ * Since ACPI or FDT will only one be available in the system, >+ * we can use acpi_generic_timer_init() here safely >+ */ >+ acpi_generic_timer_init(); >+ > arch_timer_rate = arch_timer_get_rate(); > if (!arch_timer_rate) > panic("Unable to initialise architected timer.\n"); >diff --git a/drivers/clocksource/arm_arch_timer.c >b/drivers/clocksource/arm_arch_timer.c >index 6a79fc4..612f2a0 100644 >--- a/drivers/clocksource/arm_arch_timer.c >+++ b/drivers/clocksource/arm_arch_timer.c >@@ -21,6 +21,7 @@ > #include > #include > #include >+#include > > #include > #include >@@ -370,8 +371,12 @@ arch_timer_detect_rate(void __iomem *cntbase, struct >device_node *np) > if (arch_timer_rate) > return; > >- /* Try to determine the frequency from the device tree or CNTFRQ */ >- if (of_property_read_u32(np, "clock-frequency", &arch_timer_rate)) { >+ /* >+ * Try to determine the frequency from the device tree or CNTFRQ, >+ * if ACPI is enabled, get the frequency from CNTFRQ ONLY. >+ */ >+ if (!acpi_disabled || >+ of_property_read_u32(np, "clock-frequency", &arch_timer_rate)) { > if (cntbase) > arch_timer_rate = readl_relaxed(cntbase + CNTFRQ); > else >@@ -690,28 +695,8 @@ static void __init arch_timer_common_init(void) > arch_timer_arch_init(); > } > >-static void __init arch_timer_init(struct device_node *np) >+static void __init arch_timer_init(void) > { >- int i; >- >- if (arch_timers_present & ARCH_CP15_TIMER) { >- pr_warn("arch_timer: multiple nodes in dt, skipping\n"); >- return; >- } >- >- arch_timers_present |= ARCH_CP15_TIMER; >- for (i = PHYS_SECURE_PPI; i < MAX_TIMER_PPI; i++) >- arch_timer_ppi[i] = irq_of_parse_and_map(np, i); >- arch_timer_detect_rate(NULL, np); >- >- /* >- * If we cannot rely on firmware initializing the timer registers then >- * we should use the physical timers instead. >- */ >- if (IS_ENABLED(CONFIG_ARM) && >- of_property_read_bool(np, "arm,cpu-registers-not-fw-configured")) >- arch_timer_use_virtual = false; >- > /* > * If HYP mode is available, we know that the physical timer > * has been configured to be accessible from PL1. Use it, so >@@ -730,13 +715,39 @@ static void __init arch_timer_init(struct >device_node *np) > } > } > >- arch_timer_c3stop = !of_property_read_bool(np, "always-on"); >- > arch_timer_register(); > arch_timer_common_init(); > } >-CLOCKSOURCE_OF_DECLARE(armv7_arch_timer, "arm,armv7-timer", >arch_timer_init); >-CLOCKSOURCE_OF_DECLARE(armv8_arch_timer, "arm,armv8-timer", >arch_timer_init); >+ >+static void __init arch_timer_of_init(struct device_node *np) >+{ >+ int i; >+ >+ if (arch_timers_present & ARCH_CP15_TIMER) { >+ pr_warn("arch_timer: multiple nodes in dt, skipping\n"); >+ return; >+ } >+ >+ arch_timers_present |= ARCH_CP15_TIMER; >+ for (i = PHYS_SECURE_PPI; i < MAX_TIMER_PPI; i++) >+ arch_timer_ppi[i] = irq_of_parse_and_map(np, i); >+ >+ arch_timer_detect_rate(NULL, np); >+ >+ arch_timer_c3stop = !of_property_read_bool(np, "always-on"); >+ >+ /* >+ * If we cannot rely on firmware initializing the timer registers then >+ * we should use the physical timers instead. >+ */ >+ if (IS_ENABLED(CONFIG_ARM) && >+ of_property_read_bool(np, "arm,cpu-registers-not-fw-configured")) >+ arch_timer_use_virtual = false; >+ >+ arch_timer_init(); >+} >+CLOCKSOURCE_OF_DECLARE(armv7_arch_timer, "arm,armv7-timer", >arch_timer_of_init); >+CLOCKSOURCE_OF_DECLARE(armv8_arch_timer, "arm,armv8-timer", >arch_timer_of_init); Hanjun, FYI, it seems that the tree that you have rebased the patch series has an issue determining clocksource in ARM64 introduced by this commit. http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=0 b46b8a718c6e90910a1b1b0fe797be3c167e186 Here is the fix from Catalin that already went upstream: http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/drive rs/clocksource/arm_arch_timer.c?id=d6ad36913083d683aad4e02e53580c995f1a6ede Thanks, Suravee