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[89.103.73.235]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d4fd9decbsm9222955e9.27.2025.03.20.15.24.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Mar 2025 15:24:23 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Thu, 20 Mar 2025 23:24:17 +0100 Message-Id: Subject: Re: [PATCH v12 19/28] riscv/ptrace: riscv cfi status and state via ptrace and in core files Cc: , , , , , , , , , , , , , , , , , , , , , "linux-riscv" To: "Deepak Gupta" , "Thomas Gleixner" , "Ingo Molnar" , "Borislav Petkov" , "Dave Hansen" , , "H. Peter Anvin" , "Andrew Morton" , "Liam R. Howlett" , "Vlastimil Babka" , "Lorenzo Stoakes" , "Paul Walmsley" , "Palmer Dabbelt" , "Albert Ou" , "Conor Dooley" , "Rob Herring" , "Krzysztof Kozlowski" , "Arnd Bergmann" , "Christian Brauner" , "Peter Zijlstra" , "Oleg Nesterov" , "Eric Biederman" , "Kees Cook" , "Jonathan Corbet" , "Shuah Khan" , "Jann Horn" , "Conor Dooley" From: =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= References: <20250314-v5_user_cfi_series-v12-0-e51202b53138@rivosinc.com> <20250314-v5_user_cfi_series-v12-19-e51202b53138@rivosinc.com> In-Reply-To: <20250314-v5_user_cfi_series-v12-19-e51202b53138@rivosinc.com> 2025-03-14T14:39:38-07:00, Deepak Gupta : > Expose a new register type NT_RISCV_USER_CFI for risc-v cfi status and > state. Intentionally both landing pad and shadow stack status and state > are rolled into cfi state. Creating two different NT_RISCV_USER_XXX would > not be useful and wastage of a note type. Enabling or disabling of featur= e > is not allowed via ptrace set interface. However setting `elp` state or > setting shadow stack pointer are allowed via ptrace set interface. It is > expected `gdb` might have use to fixup `elp` state or `shadow stack` > pointer. > > Signed-off-by: Deepak Gupta > --- > arch/riscv/include/uapi/asm/ptrace.h | 18 ++++++++ > arch/riscv/kernel/ptrace.c | 83 ++++++++++++++++++++++++++++++= ++++++ > include/uapi/linux/elf.h | 1 + > 3 files changed, 102 insertions(+) > > diff --git a/arch/riscv/include/uapi/asm/ptrace.h b/arch/riscv/include/ua= pi/asm/ptrace.h > index 659ea3af5680..e6571fba8a8a 100644 > --- a/arch/riscv/include/uapi/asm/ptrace.h > +++ b/arch/riscv/include/uapi/asm/ptrace.h > @@ -131,6 +131,24 @@ struct __sc_riscv_cfi_state { > unsigned long ss_ptr; /* shadow stack pointer */ > }; > =20 > +struct __cfi_status { > + /* indirect branch tracking state */ > + __u64 lp_en : 1; > + __u64 lp_lock : 1; > + __u64 elp_state : 1; > + > + /* shadow stack status */ > + __u64 shstk_en : 1; > + __u64 shstk_lock : 1; I remember there was deep hatred towards bitfields in the Linux community, have things changes? > + __u64 rsvd : sizeof(__u64) - 5; I think you meant "64 - 5". > +}; > + > +struct user_cfi_state { > + struct __cfi_status cfi_status; > + __u64 shstk_ptr; > +}; > + > #endif /* __ASSEMBLY__ */ > =20 > #endif /* _UAPI_ASM_RISCV_PTRACE_H */ > diff --git a/arch/riscv/kernel/ptrace.c b/arch/riscv/kernel/ptrace.c > @@ -224,6 +297,16 @@ static const struct user_regset riscv_user_regset[] = =3D { > .set =3D tagged_addr_ctrl_set, > }, > #endif > +#ifdef CONFIG_RISCV_USER_CFI > + [REGSET_CFI] =3D { > + .core_note_type =3D NT_RISCV_USER_CFI, > + .align =3D sizeof(__u64), > + .n =3D sizeof(struct user_cfi_state) / sizeof(__u64), > + .size =3D sizeof(__u64), Why not `size =3D sizeof(struct user_cfi_state)` and `n =3D 1`? > + .regset_get =3D riscv_cfi_get, > + .set =3D riscv_cfi_set, > + }, > +#endif [I haven't yet reviewed if a new register is the right thing to do nor looked at the rest of the patch.]