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[144.178.202.138]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-acb6ef468d3sm118642866b.136.2025.04.18.06.19.39 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 18 Apr 2025 06:19:40 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Fri, 18 Apr 2025 15:19:39 +0200 Message-Id: Cc: , , , , , , , , , <~postmarketos/upstreaming@lists.sr.ht> Subject: Re: [PATCH] ASoC: qcom: sc8280xp: enable primary mi2s From: "Luca Weiss" To: "Luca Weiss" , , "Danila Tikhonov" X-Mailer: aerc 0.20.1-0-g2ecb8770224a References: <20250203113857.34728-1-danila@jiaxyga.com> <842284b1-343f-4991-98f4-462f547ad2bc@linaro.org> <7ac9b23a-6138-46ad-8af8-fe283b765565@linaro.org> In-Reply-To: On Tue Feb 4, 2025 at 11:09 AM CET, Luca Weiss wrote: > On Tue Feb 4, 2025 at 11:08 AM CET, neil.armstrong wrote: >> On 04/02/2025 11:04, Luca Weiss wrote: >>> On Tue Feb 4, 2025 at 9:19 AM CET, neil.armstrong wrote: >>>> On 04/02/2025 00:27, Luca Weiss wrote: >>>>> On Mon Feb 3, 2025 at 5:33 PM CET, Danila Tikhonov wrote: >>>>>> On 03/02/2025 17:23, neil.armstrong@linaro.org wrote: >>>>>>> On 03/02/2025 12:38, Danila Tikhonov wrote: >>>>>>>> When using primary mi2s on sc8280xp-compatible SoCs, the correct c= lock >>>>>>>> needs to get enabled to be able to use the mi2s interface. >>>>>>>> >>>>>>>> Signed-off-by: Danila Tikhonov >>>>>>>> --- >>>>>>>> =C2=A0 sound/soc/qcom/sc8280xp.c | 13 +++++++++++++ >>>>>>>> =C2=A0 1 file changed, 13 insertions(+) >>>>>>>> >>>>>>>> diff --git a/sound/soc/qcom/sc8280xp.c b/sound/soc/qcom/sc8280xp.c >>>>>>>> index 311377317176..03687de1ebb0 100644 >>>>>>>> --- a/sound/soc/qcom/sc8280xp.c >>>>>>>> +++ b/sound/soc/qcom/sc8280xp.c >>>>>>>> @@ -14,6 +14,8 @@ >>>>>>>> =C2=A0 #include "common.h" >>>>>>>> =C2=A0 #include "sdw.h" >>>>>>>> =C2=A0 +#define MI2S_BCLK_RATE=C2=A0=C2=A0=C2=A0 1536000 >>>>>>>> + >>>>>>>> =C2=A0 struct sc8280xp_snd_data { >>>>>>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 bool stream_prepared[AFE_PORT_MAX= ]; >>>>>>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 struct snd_soc_card *card; >>>>>>>> @@ -25,13 +27,24 @@ struct sc8280xp_snd_data { >>>>>>>> =C2=A0 =C2=A0 static int sc8280xp_snd_init(struct snd_soc_pcm_ru= ntime *rtd) >>>>>>>> =C2=A0 { >>>>>>>> +=C2=A0=C2=A0=C2=A0 unsigned int codec_dai_fmt =3D SND_SOC_DAIFMT_= BC_FC; >>>>>>>> +=C2=A0=C2=A0=C2=A0 unsigned int fmt =3D SND_SOC_DAIFMT_BP_FP; >>>>>>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 struct sc8280xp_snd_data *data = =3D >>>>>>>> snd_soc_card_get_drvdata(rtd->card); >>>>>>>> +=C2=A0=C2=A0=C2=A0 struct snd_soc_dai *codec_dai =3D snd_soc_rtd_= to_codec(rtd, 0); >>>>>>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 struct snd_soc_dai *cpu_dai =3D s= nd_soc_rtd_to_cpu(rtd, 0); >>>>>>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 struct snd_soc_card *card =3D rtd= ->card; >>>>>>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 struct snd_soc_jack *dp_jack=C2= =A0 =3D NULL; >>>>>>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 int dp_pcm_id =3D 0; >>>>>>>> =C2=A0 =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 switch (cpu_dai->id) { >>>>>>>> +=C2=A0=C2=A0=C2=A0 case PRIMARY_MI2S_RX: >>>>>>>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 codec_dai_fmt |=3D SND= _SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_I2S; >>>>>>>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 snd_soc_dai_set_sysclk= (cpu_dai, >>>>>>>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0 Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT, >>>>>>>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0 MI2S_BCLK_RATE, SNDRV_PCM_STREAM_PLAYBACK); >>>>>>> >>>>>>> How is this possible ? sc8280xp uses the q6prm clock driver, and >>>>>>> there's no >>>>>>> way this call sets the Q6PRM_LPASS_CLK_ID_PRI_MI2S_IBIT, or I total= ly >>>>>>> missed >>>>>>> something. >>>>>>> >>>>>>> And prm is neither a dai nor has the set_sysclk callback. >>>>>>> >>>>>>> Neil >>>>>>> >>>>>> Oh, thanks for the answer. >>>>>> >>>>>> This comes from qcm6490 compatibility. Actually it is needed for >>>>>> Nothing Phone (1) and Luca Weiss just suggested me to use >>>>>> qcom,qcm6490-idp-sndcard like do they do it for FP5. (SM7325 is the >>>>>> closest to QCM6490): >>>>>> https://github.com/sc7280-mainline/linux/pull/5#discussion_r18489847= 88 >>>>>> Actually I also think it is a bit incorrect. >>>>> >>>>> For reference, this is coming from this and following: >>>>> https://lore.kernel.org/linux-arm-msm/e8a24709-de96-4d09-ba00-1e084a6= 56c68@kernel.org/ >>>> >>>> Sure, but do you use sound/soc/qcom/sc8280xp.c ? it's designed for aud= ioreach >>>> compatible audio architecture (post sm8250). >>>=20 >>> I would've also thought qcm6490-idp and qcm6490-rb3gen2 are >>> pre-audioreach, so sm8250.c would be a better match - but these two >>> devices already use sc8280xp.c driver for some reason? >> >> I think they were added to sc8280xp.c because it has the logic to change >> the card name and some other tweaks for record channels setup, >> but it can be easily added to sm8250.c. > > This is probably a better idea then... FYI I've sent these patches now, confirmed with DisplayPort audio on QCM6490 Fairphone 5 https://lore.kernel.org/linux-arm-msm/20250418-fp5-dp-sound-v2-2-05d65f084b= 05@fairphone.com/ + following Regards Luca > >> >> Neil >> >>>=20 >>> Maybe someone with more insight on these devices can help clarify this? >>> I'll also need this for qcm6490-fairphone-fp5 soon. >>>=20 >>> Regards Luca >>>=20 >>>> >>>> sound/soc/qcom/sm8250.c has already support for PRIMARY_MI2S_RX via >>>> the Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT, and it compatible with the previ= ous >>>> audio architecture (non audioreach). >>>> >>>> Neil >>>> >>>>> >>>>> Regards >>>>> Luca >>>>> >>>>>> >>>>>> --- >>>>>> Regards, >>>>>> Danila >>>>>>>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 snd_soc_dai_set_fmt(cp= u_dai, fmt); >>>>>>>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 snd_soc_dai_set_fmt(co= dec_dai, codec_dai_fmt); >>>>>>>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 break; >>>>>>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 case WSA_CODEC_DMA_RX_0: >>>>>>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 case WSA_CODEC_DMA_RX_1: >>>>>>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 /* >>>>>>> >>>>> >>>=20